mirror of https://github.com/xemu-project/xemu.git
target/ppc: Implement breakpoint debug facility for v2.07S
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -102,6 +102,33 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
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ppc_maybe_interrupt(env);
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}
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#if defined(TARGET_PPC64)
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void ppc_update_ciabr(CPUPPCState *env)
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{
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CPUState *cs = env_cpu(env);
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target_ulong ciabr = env->spr[SPR_CIABR];
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target_ulong ciea, priv;
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ciea = ciabr & PPC_BITMASK(0, 61);
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priv = ciabr & PPC_BITMASK(62, 63);
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if (env->ciabr_breakpoint) {
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cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint);
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env->ciabr_breakpoint = NULL;
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}
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if (priv) {
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cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint);
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}
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}
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void ppc_store_ciabr(CPUPPCState *env, target_ulong val)
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{
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env->spr[SPR_CIABR] = val;
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ppc_update_ciabr(env);
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}
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#endif
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#endif
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static inline void fpscr_set_rounding_mode(CPUPPCState *env)
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@ -1137,6 +1137,7 @@ struct CPUArchState {
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/* MMU context, only relevant for full system emulation */
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#if defined(TARGET_PPC64)
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ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
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struct CPUBreakpoint *ciabr_breakpoint;
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#endif
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target_ulong sr[32]; /* segment registers */
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uint32_t nb_BATs; /* number of BATs */
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@ -1403,6 +1404,8 @@ void ppc_translate_init(void);
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#if !defined(CONFIG_USER_ONLY)
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void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
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void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
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void ppc_update_ciabr(CPUPPCState *env);
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void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
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#endif /* !defined(CONFIG_USER_ONLY) */
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void ppc_store_msr(CPUPPCState *env, target_ulong value);
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@ -5127,7 +5127,7 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env)
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spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
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SPR_NOACCESS, SPR_NOACCESS,
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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&spr_read_generic, &spr_write_ciabr,
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KVM_REG_PPC_CIABR, 0x00000000);
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}
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@ -7159,6 +7159,7 @@ static void ppc_cpu_reset_hold(Object *obj)
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env->nip = env->hreset_vector | env->excp_prefix;
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if (tcg_enabled()) {
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cpu_breakpoint_remove_all(s, BP_CPU);
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if (env->mmu_model != POWERPC_MMU_REAL) {
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ppc_tlb_invalidate_all(env);
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}
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@ -7346,6 +7347,8 @@ static const struct TCGCPUOps ppc_tcg_ops = {
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.cpu_exec_exit = ppc_cpu_exec_exit,
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.do_unaligned_access = ppc_cpu_do_unaligned_access,
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.do_transaction_failed = ppc_cpu_do_transaction_failed,
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.debug_excp_handler = ppc_cpu_debug_excp_handler,
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.debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
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#endif /* !CONFIG_USER_ONLY */
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};
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#endif /* CONFIG_TCG */
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@ -3257,5 +3257,47 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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cs->exception_index = POWERPC_EXCP_MCHECK;
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cpu_loop_exit_restore(cs, retaddr);
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}
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void ppc_cpu_debug_excp_handler(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cs->env_ptr;
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if (env->insns_flags2 & PPC2_ISA207S) {
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if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) {
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raise_exception_err(env, POWERPC_EXCP_TRACE,
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PPC_BIT(33) | PPC_BIT(43));
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}
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}
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#endif
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}
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bool ppc_cpu_debug_check_breakpoint(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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CPUPPCState *env = cs->env_ptr;
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if (env->insns_flags2 & PPC2_ISA207S) {
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target_ulong priv;
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priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63);
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switch (priv) {
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case 0x1: /* problem */
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return env->msr & ((target_ulong)1 << MSR_PR);
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case 0x2: /* supervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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!(env->msr & ((target_ulong)1 << MSR_HV)));
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case 0x3: /* hypervisor */
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return (!(env->msr & ((target_ulong)1 << MSR_PR)) &&
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(env->msr & ((target_ulong)1 << MSR_HV)));
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default:
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g_assert_not_reached();
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}
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}
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#endif
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return false;
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}
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#endif /* CONFIG_TCG */
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#endif /* !CONFIG_USER_ONLY */
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@ -25,6 +25,7 @@ DEF_HELPER_1(hrfid, void, env)
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DEF_HELPER_2(rfebb, void, env, tl)
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DEF_HELPER_2(store_lpcr, void, env, tl)
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DEF_HELPER_2(store_pcr, void, env, tl)
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DEF_HELPER_2(store_ciabr, void, env, tl)
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DEF_HELPER_2(store_mmcr0, void, env, tl)
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DEF_HELPER_2(store_mmcr1, void, env, tl)
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DEF_HELPER_3(store_pmc, void, env, i32, i64)
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@ -301,6 +301,8 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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void ppc_cpu_debug_excp_handler(CPUState *cs);
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bool ppc_cpu_debug_check_breakpoint(CPUState *cs);
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#endif
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FIELD(GER_MSK, XMSK, 0, 4)
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@ -313,6 +313,10 @@ static int cpu_post_load(void *opaque, int version_id)
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post_load_update_msr(env);
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if (tcg_enabled()) {
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/* Re-set breaks based on regs */
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#if defined(TARGET_PPC64)
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ppc_update_ciabr(env);
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#endif
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pmu_mmcr01_updated(env);
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}
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@ -199,6 +199,11 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value)
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env->spr[SPR_PCR] = value & pcc->pcr_mask;
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}
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void helper_store_ciabr(CPUPPCState *env, target_ulong value)
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{
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ppc_store_ciabr(env, value);
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}
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/*
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* DPDES register is shared. Each bit reflects the state of the
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* doorbell interrupt of a thread of the same core.
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@ -159,6 +159,7 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn);
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#ifdef TARGET_PPC64
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void spr_read_cfar(DisasContext *ctx, int gprn, int sprn);
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void spr_write_cfar(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ureg(DisasContext *ctx, int sprn, int gprn);
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void spr_read_purr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_purr(DisasContext *ctx, int sprn, int gprn);
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@ -557,8 +557,9 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
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tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
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}
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/* CFAR */
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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/* Debug facilities */
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/* CFAR */
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void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
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{
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tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
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@ -568,6 +569,13 @@ void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
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{
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tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
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}
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/* Breakpoint */
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void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn)
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{
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translator_io_start(&ctx->base);
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gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]);
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}
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
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/* CTR */
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