ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

tcg/tci: Merge extension operations 

This includes ext8s, ext8u, ext16s, ext16u.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 12:21:18 -10:00
parent dd2bb20e41
commit 13a1d64045
1 changed files with 8 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
tcg/tci.c
View File

@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break; break;
#endif /* TCG_TARGET_REG_BITS == 32 */ #endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i32: CASE_32_64(ext8s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1); tci_write_reg(regs, t0, (int8_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext16s_i32 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i32: CASE_32_64(ext16s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1); tci_write_reg(regs, t0, (int16_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext8u_i32 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
case INDEX_op_ext8u_i32: CASE_32_64(ext8u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1); tci_write_reg(regs, t0, (uint8_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext16u_i32 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i32: CASE_32_64(ext16u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1); tci_write_reg(regs, t0, (uint16_t)t1);
@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue; continue;
} }
break; break;
#if TCG_TARGET_HAS_ext8u_i64
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64 #if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64: case INDEX_op_ext32s_i64:
#endif #endif