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target/ppc: Fix gen_priv_exception error value in mfspr/mtspr 

The code in linux-user/ppc/cpu_loop.c expects POWERPC_EXCP_PRIV
exception with error POWERPC_EXCP_PRIV_OPC or POWERPC_EXCP_PRIV_REG,
while POWERPC_EXCP_INVAL_SPR is expected in POWERPC_EXCP_INVAL
exceptions. This mismatch caused an EXCP_DUMP with the message "Unknown
privilege violation (03)", as seen in [1].

[1] https://gitlab.com/qemu-project/qemu/-/issues/588

Fixes: 9b2fadda3e ("ppc: Rework generation of priv and inval interrupts")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/588
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220627141104.669152-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Matheus Ferst 2022-06-27 11:10:59 -03:00 committed by Daniel Henrique Barboza
parent 1a42c69237
commit 1315eed69d
1 changed files with 4 additions and 4 deletions
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8
target/ppc/translate.c
View File

@ -4789,11 +4789,11 @@ static inline void gen_op_mfspr(DisasContext *ctx)
*/
if (sprn & 0x10) {
if (ctx->pr) {
gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
}
}
@ -4976,11 +4976,11 @@ static void gen_mtspr(DisasContext *ctx)
*/
if (sprn & 0x10) {
if (ctx->pr) {
gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
if (ctx->pr || sprn == 0) {
gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
}
}