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target-alpha: Fix ret instruction 

Hopefully pine doesn't corrupt this patch, I've had problems recently.

For an alpha "ret" instruction, of the type
     ret $26

The return was being ignored.  This is because in translate.c
register $26 (the return address) was being over-written with the current
PC before it could be jumped to.  Thus the ret was ignored.

This patch just re-orders things so the return address is processed before
it is over-written with the current PC.

(Vince Weaver)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5638 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-11-06 09:16:57 +00:00
parent f49e58dc64
commit 1304ca878a
1 changed files with 2 additions and 2 deletions
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4
target-alpha/translate.c
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@ -1634,12 +1634,12 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break;
#endif
case 0x1A:
if (ra != 31)
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
if (rb != 31)
tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
else
tcg_gen_movi_i64(cpu_pc, 0);
if (ra != 31)
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
/* Those four jumps only differ by the branch prediction hint */
switch (fn2) {
case 0x0: