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xilinx_intc: Fix writes into MER register 

The MER register only has two valid bits. This is now used by
the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits before
writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Edgar: Untabified]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Guenter Roeck 2014-04-25 08:39:47 -07:00 committed by Edgar E. Iglesias
parent 6d35556caa
commit 12f7fb6086
1 changed files with 3 additions and 0 deletions
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3
hw/intc/xilinx_intc.c
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@ -121,6 +121,9 @@ pic_write(void *opaque, hwaddr addr,
case R_CIE: case R_CIE:
p->regs[R_IER] &= ~value; /* Atomic clear ie. */ p->regs[R_IER] &= ~value; /* Atomic clear ie. */
break; break;
case R_MER:
p->regs[R_MER] = value & 0x3;
break;
case R_ISR: case R_ISR:
if ((p->regs[R_MER] & 2)) { if ((p->regs[R_MER] & 2)) {
break; break;