mirror of https://github.com/xemu-project/xemu.git
hw/intc/arm_gicv3: Add cast to match the documentation
The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICC_AP[0/1]R<n>_EL2 are reserved.
Add an explicit cast to match the documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: 28cca59c46
("hw/intc/arm_gicv3: Add NMI handling CPU interface registers")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1170,7 +1170,7 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
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if (nmi) {
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cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI;
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} else {
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cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit);
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cs->icc_apr[cs->hppi.grp][regno] |= (1U << regbit);
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}
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if (irq < GIC_INTERNAL) {
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