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target-alpha: Rationalize internal processor registers. 

Delete all the code that tried to emulate the real IPRs of some
unnamed CPU.  Replace those with just 3 slots that we can use to
communicate trap information between the helper functions that
signal exceptions and the OS trap handler.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2011-05-20 13:30:00 -07:00 committed by Richard Henderson
parent 508b43eaf3
commit 129d8aa575
6 changed files with 23 additions and 562 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
linux-user/main.c
View File

@ -2524,9 +2524,9 @@ void cpu_loop (CPUState *env)
env->lock_addr = -1;
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
info.si_code = (page_get_flags(env->ipr[IPR_EXC_ADDR]) & PAGE_VALID
info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
info._sifields._sigfault._addr = env->trap_arg0;
queue_signal(env, info.si_signo, &info);
break;
case EXCP_DTB_MISS_PAL:
@ -2550,7 +2550,7 @@ void cpu_loop (CPUState *env)
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
info.si_code = TARGET_BUS_ADRALN;
info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
info._sifields._sigfault._addr = env->trap_arg0;
queue_signal(env, info.si_signo, &info);
break;
case EXCP_OPCDEC:

145
target-alpha/cpu.h
View File

@ -192,131 +192,6 @@ enum {
#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
/* Internal processor registers */
/* XXX: TOFIX: most of those registers are implementation dependant */
enum {
#if defined(CONFIG_USER_ONLY)
IPR_EXC_ADDR,
IPR_EXC_SUM,
IPR_EXC_MASK,
#else
/* Ebox IPRs */
IPR_CC = 0xC0, /* 21264 */
IPR_CC_CTL = 0xC1, /* 21264 */
#define IPR_CC_CTL_ENA_SHIFT 32
#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
IPR_VA = 0xC2, /* 21264 */
IPR_VA_CTL = 0xC4, /* 21264 */
#define IPR_VA_CTL_VA_48_SHIFT 1
#define IPR_VA_CTL_VPTB_SHIFT 30
IPR_VA_FORM = 0xC3, /* 21264 */
/* Ibox IPRs */
IPR_ITB_TAG = 0x00, /* 21264 */
IPR_ITB_PTE = 0x01, /* 21264 */
IPR_ITB_IAP = 0x02,
IPR_ITB_IA = 0x03, /* 21264 */
IPR_ITB_IS = 0x04, /* 21264 */
IPR_PMPC = 0x05,
IPR_EXC_ADDR = 0x06, /* 21264 */
IPR_IVA_FORM = 0x07, /* 21264 */
IPR_CM = 0x09, /* 21264 */
#define IPR_CM_SHIFT 3
#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */
IPR_IER = 0x0A, /* 21264 */
#define IPR_IER_MASK 0x0000007fffffe000ULL
IPR_IER_CM = 0x0B, /* 21264: = CM | IER */
IPR_SIRR = 0x0C, /* 21264 */
#define IPR_SIRR_SHIFT 14
#define IPR_SIRR_MASK 0x7fff
IPR_ISUM = 0x0D, /* 21264 */
IPR_HW_INT_CLR = 0x0E, /* 21264 */
IPR_EXC_SUM = 0x0F,
IPR_PAL_BASE = 0x10,
IPR_I_CTL = 0x11,
#define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */
#define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */
#define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */
#define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */
#define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */
#define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */
#define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */
#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
IPR_I_STAT = 0x16, /* 21264 */
IPR_IC_FLUSH = 0x13, /* 21264 */
IPR_IC_FLUSH_ASM = 0x12, /* 21264 */
IPR_CLR_MAP = 0x15,
IPR_SLEEP = 0x17,
IPR_PCTX = 0x40,
IPR_PCTX_ASN = 0x01, /* field */
#define IPR_PCTX_ASN_SHIFT 39
IPR_PCTX_ASTER = 0x02, /* field */
#define IPR_PCTX_ASTER_SHIFT 5
IPR_PCTX_ASTRR = 0x04, /* field */
#define IPR_PCTX_ASTRR_SHIFT 9
IPR_PCTX_PPCE = 0x08, /* field */
#define IPR_PCTX_PPCE_SHIFT 1
IPR_PCTX_FPE = 0x10, /* field */
#define IPR_PCTX_FPE_SHIFT 2
IPR_PCTX_ALL = 0x5f, /* all fields */
IPR_PCTR_CTL = 0x14, /* 21264 */
/* Mbox IPRs */
IPR_DTB_TAG0 = 0x20, /* 21264 */
IPR_DTB_TAG1 = 0xA0, /* 21264 */
IPR_DTB_PTE0 = 0x21, /* 21264 */
IPR_DTB_PTE1 = 0xA1, /* 21264 */
IPR_DTB_ALTMODE = 0xA6,
IPR_DTB_ALTMODE0 = 0x26, /* 21264 */
#define IPR_DTB_ALTMODE_MASK 3
IPR_DTB_IAP = 0xA2,
IPR_DTB_IA = 0xA3, /* 21264 */
IPR_DTB_IS0 = 0x24,
IPR_DTB_IS1 = 0xA4,
IPR_DTB_ASN0 = 0x25, /* 21264 */
IPR_DTB_ASN1 = 0xA5, /* 21264 */
#define IPR_DTB_ASN_SHIFT 56
IPR_MM_STAT = 0x27, /* 21264 */
IPR_M_CTL = 0x28, /* 21264 */
#define IPR_M_CTL_SPE_SHIFT 1
#define IPR_M_CTL_SPE_MASK 7
IPR_DC_CTL = 0x29, /* 21264 */
IPR_DC_STAT = 0x2A, /* 21264 */
/* Cbox IPRs */
IPR_C_DATA = 0x2B,
IPR_C_SHIFT = 0x2C,
IPR_ASN,
IPR_ASTEN,
IPR_ASTSR,
IPR_DATFX,
IPR_ESP,
IPR_FEN,
IPR_IPIR,
IPR_IPL,
IPR_KSP,
IPR_MCES,
IPR_PERFMON,
IPR_PCBB,
IPR_PRBR,
IPR_PTBR,
IPR_SCBB,
IPR_SISR,
IPR_SSP,
IPR_SYSPTBR,
IPR_TBCHK,
IPR_TBIA,
IPR_TBIAP,
IPR_TBIS,
IPR_TBISD,
IPR_TBISI,
IPR_USP,
IPR_VIRBND,
IPR_VPTB,
IPR_WHAMI,
IPR_ALT_MODE,
#endif
IPR_LAST,
};
/* MMU modes definitions */
/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
@ -350,8 +225,6 @@ struct CPUAlphaState {
uint64_t ir[31];
float64 fir[31];
uint64_t pc;
uint64_t ipr[IPR_LAST];
uint64_t ps;
uint64_t unique;
uint64_t lock_addr;
uint64_t lock_st_addr;
@ -366,10 +239,18 @@ struct CPUAlphaState {
uint8_t fpcr_dnod;
uint8_t fpcr_undz;
/* Used for HW_LD / HW_ST */
uint8_t saved_mode;
/* For RC and RS */
/* The Internal Processor Registers. Some of these we assume always
exist for use in user-mode. */
uint8_t ps;
uint8_t intr_flag;
uint8_t pal_mode;
/* These pass data from the exception logic in the translator and
helpers to the OS entry point. This is used for both system
emulation and user-mode. */
uint64_t trap_arg0;
uint64_t trap_arg1;
uint64_t trap_arg2;
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* temporary fixed-point registers
@ -381,8 +262,6 @@ struct CPUAlphaState {
/* Those resources are used only in Qemu core */
CPU_COMMON
uint32_t hflags;
int error_code;
uint32_t features;
@ -492,8 +371,6 @@ void do_interrupt (CPUState *env);
uint64_t cpu_alpha_load_fpcr (CPUState *env);
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)

349
target-alpha/helper.c
View File

@ -168,8 +168,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
env->exception_index = EXCP_ITB_MISS;
else
env->exception_index = EXCP_DFAULT;
env->ipr[IPR_EXC_ADDR] = address;
env->trap_arg0 = address;
return 1;
}
@ -188,352 +187,12 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
uint32_t opc;
if (rw == 2) {
/* Instruction translation buffer miss */
env->exception_index = EXCP_ITB_MISS;
} else {
if (env->ipr[IPR_EXC_ADDR] & 1)
env->exception_index = EXCP_DTB_MISS_PAL;
else
env->exception_index = EXCP_DTB_MISS_NATIVE;
opc = (ldl_code(env->pc) >> 21) << 4;
if (rw) {
opc |= 0x9;
} else {
opc |= 0x4;
}
env->ipr[IPR_MM_STAT] = opc;
}
return 1;
}
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp)
{
uint64_t hwpcb;
int ret = 0;
hwpcb = env->ipr[IPR_PCBB];
switch (iprn) {
case IPR_ASN:
if (env->features & FEATURE_ASN)
*valp = env->ipr[IPR_ASN];
else
*valp = 0;
break;
case IPR_ASTEN:
*valp = ((int64_t)(env->ipr[IPR_ASTEN] << 60)) >> 60;
break;
case IPR_ASTSR:
*valp = ((int64_t)(env->ipr[IPR_ASTSR] << 60)) >> 60;
break;
case IPR_DATFX:
/* Write only */
ret = -1;
break;
case IPR_ESP:
if (env->features & FEATURE_SPS)
*valp = env->ipr[IPR_ESP];
else
*valp = ldq_raw(hwpcb + 8);
break;
case IPR_FEN:
*valp = ((int64_t)(env->ipr[IPR_FEN] << 63)) >> 63;
break;
case IPR_IPIR:
/* Write-only */
ret = -1;
break;
case IPR_IPL:
*valp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
break;
case IPR_KSP:
if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
ret = -1;
} else {
if (env->features & FEATURE_SPS)
*valp = env->ipr[IPR_KSP];
else
*valp = ldq_raw(hwpcb + 0);
}
break;
case IPR_MCES:
*valp = ((int64_t)(env->ipr[IPR_MCES] << 59)) >> 59;
break;
case IPR_PERFMON:
/* Implementation specific */
*valp = 0;
break;
case IPR_PCBB:
*valp = ((int64_t)env->ipr[IPR_PCBB] << 16) >> 16;
break;
case IPR_PRBR:
*valp = env->ipr[IPR_PRBR];
break;
case IPR_PTBR:
*valp = env->ipr[IPR_PTBR];
break;
case IPR_SCBB:
*valp = (int64_t)((int32_t)env->ipr[IPR_SCBB]);
break;
case IPR_SIRR:
/* Write-only */
ret = -1;
break;
case IPR_SISR:
*valp = (int64_t)((int16_t)env->ipr[IPR_SISR]);
case IPR_SSP:
if (env->features & FEATURE_SPS)
*valp = env->ipr[IPR_SSP];
else
*valp = ldq_raw(hwpcb + 16);
break;
case IPR_SYSPTBR:
if (env->features & FEATURE_VIRBND)
*valp = env->ipr[IPR_SYSPTBR];
else
ret = -1;
break;
case IPR_TBCHK:
if ((env->features & FEATURE_TBCHK)) {
/* XXX: TODO */
*valp = 0;
ret = -1;
} else {
ret = -1;
}
break;
case IPR_TBIA:
/* Write-only */
ret = -1;
break;
case IPR_TBIAP:
/* Write-only */
ret = -1;
break;
case IPR_TBIS:
/* Write-only */
ret = -1;
break;
case IPR_TBISD:
/* Write-only */
ret = -1;
break;
case IPR_TBISI:
/* Write-only */
ret = -1;
break;
case IPR_USP:
if (env->features & FEATURE_SPS)
*valp = env->ipr[IPR_USP];
else
*valp = ldq_raw(hwpcb + 24);
break;
case IPR_VIRBND:
if (env->features & FEATURE_VIRBND)
*valp = env->ipr[IPR_VIRBND];
else
ret = -1;
break;
case IPR_VPTB:
*valp = env->ipr[IPR_VPTB];
break;
case IPR_WHAMI:
*valp = env->ipr[IPR_WHAMI];
break;
default:
/* Invalid */
ret = -1;
break;
}
return ret;
}
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp)
{
uint64_t hwpcb, tmp64;
uint8_t tmp8;
int ret = 0;
hwpcb = env->ipr[IPR_PCBB];
switch (iprn) {
case IPR_ASN:
/* Read-only */
ret = -1;
break;
case IPR_ASTEN:
tmp8 = ((int8_t)(env->ipr[IPR_ASTEN] << 4)) >> 4;
*oldvalp = tmp8;
tmp8 &= val & 0xF;
tmp8 |= (val >> 4) & 0xF;
env->ipr[IPR_ASTEN] &= ~0xF;
env->ipr[IPR_ASTEN] |= tmp8;
ret = 1;
break;
case IPR_ASTSR:
tmp8 = ((int8_t)(env->ipr[IPR_ASTSR] << 4)) >> 4;
*oldvalp = tmp8;
tmp8 &= val & 0xF;
tmp8 |= (val >> 4) & 0xF;
env->ipr[IPR_ASTSR] &= ~0xF;
env->ipr[IPR_ASTSR] |= tmp8;
ret = 1;
case IPR_DATFX:
env->ipr[IPR_DATFX] &= ~0x1;
env->ipr[IPR_DATFX] |= val & 1;
tmp64 = ldq_raw(hwpcb + 56);
tmp64 &= ~0x8000000000000000ULL;
tmp64 |= (val & 1) << 63;
stq_raw(hwpcb + 56, tmp64);
break;
case IPR_ESP:
if (env->features & FEATURE_SPS)
env->ipr[IPR_ESP] = val;
else
stq_raw(hwpcb + 8, val);
break;
case IPR_FEN:
env->ipr[IPR_FEN] = val & 1;
tmp64 = ldq_raw(hwpcb + 56);
tmp64 &= ~1;
tmp64 |= val & 1;
stq_raw(hwpcb + 56, tmp64);
break;
case IPR_IPIR:
/* XXX: TODO: Send IRQ to CPU #ir[16] */
break;
case IPR_IPL:
*oldvalp = ((int64_t)(env->ipr[IPR_IPL] << 59)) >> 59;
env->ipr[IPR_IPL] &= ~0x1F;
env->ipr[IPR_IPL] |= val & 0x1F;
/* XXX: may issue an interrupt or ASR _now_ */
ret = 1;
break;
case IPR_KSP:
if (!(env->ipr[IPR_EXC_ADDR] & 1)) {
ret = -1;
} else {
if (env->features & FEATURE_SPS)
env->ipr[IPR_KSP] = val;
else
stq_raw(hwpcb + 0, val);
}
break;
case IPR_MCES:
env->ipr[IPR_MCES] &= ~((val & 0x7) | 0x18);
env->ipr[IPR_MCES] |= val & 0x18;
break;
case IPR_PERFMON:
/* Implementation specific */
*oldvalp = 0;
ret = 1;
break;
case IPR_PCBB:
/* Read-only */
ret = -1;
break;
case IPR_PRBR:
env->ipr[IPR_PRBR] = val;
break;
case IPR_PTBR:
/* Read-only */
ret = -1;
break;
case IPR_SCBB:
env->ipr[IPR_SCBB] = (uint32_t)val;
break;
case IPR_SIRR:
if (val & 0xF) {
env->ipr[IPR_SISR] |= 1 << (val & 0xF);
/* XXX: request a software interrupt _now_ */
}
break;
case IPR_SISR:
/* Read-only */
ret = -1;
break;
case IPR_SSP:
if (env->features & FEATURE_SPS)
env->ipr[IPR_SSP] = val;
else
stq_raw(hwpcb + 16, val);
break;
case IPR_SYSPTBR:
if (env->features & FEATURE_VIRBND)
env->ipr[IPR_SYSPTBR] = val;
else
ret = -1;
break;
case IPR_TBCHK:
/* Read-only */
ret = -1;
break;
case IPR_TBIA:
tlb_flush(env, 1);
break;
case IPR_TBIAP:
tlb_flush(env, 1);
break;
case IPR_TBIS:
tlb_flush_page(env, val);
break;
case IPR_TBISD:
tlb_flush_page(env, val);
break;
case IPR_TBISI:
tlb_flush_page(env, val);
break;
case IPR_USP:
if (env->features & FEATURE_SPS)
env->ipr[IPR_USP] = val;
else
stq_raw(hwpcb + 24, val);
break;
case IPR_VIRBND:
if (env->features & FEATURE_VIRBND)
env->ipr[IPR_VIRBND] = val;
else
ret = -1;
break;
case IPR_VPTB:
env->ipr[IPR_VPTB] = val;
break;
case IPR_WHAMI:
/* Read-only */
ret = -1;
break;
default:
/* Invalid */
ret = -1;
break;
}
return ret;
return 0;
}
void do_interrupt (CPUState *env)
{
int excp;
env->ipr[IPR_EXC_ADDR] = env->pc | 1;
excp = env->exception_index;
env->exception_index = -1;
env->error_code = 0;
/* XXX: disable interrupts and memory mapping */
if (env->ipr[IPR_PAL_BASE] != -1ULL) {
/* We use native PALcode */
env->pc = env->ipr[IPR_PAL_BASE] + excp;
} else {
/* We use emulated PALcode */
abort();
/* Emulate REI */
env->pc = env->ipr[IPR_EXC_ADDR] & ~7;
env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1;
/* XXX: re-enable interrupts and memory mapping */
}
abort();
}
#endif
@ -548,7 +207,7 @@ void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
};
int i;
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS " TARGET_FMT_lx "\n",
cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n",
env->pc, env->ps);
for (i = 0; i < 31; i++) {
cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,

2
target-alpha/helper.h
View File

@ -101,8 +101,6 @@ DEF_HELPER_1(ieee_input_s, i64, i64)
#if !defined (CONFIG_USER_ONLY)
DEF_HELPER_1(hw_ret, void, i64)
DEF_HELPER_2(mfpr, i64, int, i64)
DEF_HELPER_2(mtpr, void, int, i64)
DEF_HELPER_1(ldl_phys, i64, i64)
DEF_HELPER_1(ldq_phys, i64, i64)

19
target-alpha/op_helper.c
View File

@ -373,7 +373,7 @@ void helper_fp_exc_raise(uint32_t exc, uint32_t regno)
if (exc) {
uint32_t hw_exc = 0;
env->ipr[IPR_EXC_MASK] |= 1ull << regno;
env->trap_arg1 = 1ull << regno;
if (exc & float_flag_invalid) {
hw_exc |= EXC_M_INV;
@ -1159,25 +1159,10 @@ uint64_t helper_cvtqg (uint64_t a)
void helper_hw_ret (uint64_t a)
{
env->pc = a & ~3;
env->ipr[IPR_EXC_ADDR] = a & 1;
env->pal_mode = a & 1;
env->intr_flag = 0;
env->lock_addr = -1;
}
uint64_t helper_mfpr (int iprn, uint64_t val)
{
uint64_t tmp;
if (cpu_alpha_mfpr(env, iprn, &tmp) == 0)
val = tmp;
return val;
}
void helper_mtpr (int iprn, uint64_t val)
{
cpu_alpha_mtpr(env, iprn, val, NULL);
}
#endif
/*****************************************************************************/

64
target-alpha/translate.c
View File

@ -2576,18 +2576,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x19:
/* HW_MFPR (PALcode) */
#if defined (CONFIG_USER_ONLY)
goto invalid_opc;
#else
if (!ctx->pal_mode)
goto invalid_opc;
if (ra != 31) {
TCGv tmp = tcg_const_i32(insn & 0xFF);
gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]);
tcg_temp_free(tmp);
}
break;
#endif
case 0x1A:
/* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch
prediction stack action, which of course we don't implement. */
@ -2856,25 +2845,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1D:
/* HW_MTPR (PALcode) */
#if defined (CONFIG_USER_ONLY)
goto invalid_opc;
#else
if (!ctx->pal_mode)
goto invalid_opc;
else {
TCGv tmp1 = tcg_const_i32(insn & 0xFF);
if (ra != 31)
gen_helper_mtpr(tmp1, cpu_ir[ra]);
else {
TCGv tmp2 = tcg_const_i64(0);
gen_helper_mtpr(tmp1, tmp2);
tcg_temp_free(tmp2);
}
tcg_temp_free(tmp1);
ret = EXIT_PC_STALE;
}
break;
#endif
case 0x1E:
/* HW_RET (PALcode) */
#if defined (CONFIG_USER_ONLY)
@ -2887,7 +2858,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
address from EXC_ADDR. This turns out to be useful for our
emulation PALcode, so continue to accept it. */
TCGv tmp = tcg_temp_new();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, ipr[IPR_EXC_ADDR]));
/* FIXME: Get exc_addr. */
gen_helper_hw_ret(tmp);
tcg_temp_free(tmp);
} else {
@ -3131,7 +3102,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
ctx.mem_idx = 0;
#else
ctx.mem_idx = ((env->ps >> 3) & 3);
ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
ctx.pal_mode = env->pal_mode;
#endif
/* ??? Every TB begins with unset rounding mode, to be initialized on
@ -3297,42 +3268,13 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
env->implver = implver;
env->amask = amask;
env->ps = 0x1F00;
#if defined (CONFIG_USER_ONLY)
env->ps |= 1 << 3;
env->ps = 1 << 3;
cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
#endif
env->lock_addr = -1;
/* Initialize IPR */
#if defined (CONFIG_USER_ONLY)
env->ipr[IPR_EXC_ADDR] = 0;
env->ipr[IPR_EXC_SUM] = 0;
env->ipr[IPR_EXC_MASK] = 0;
#else
{
// uint64_t hwpcb;
// hwpcb = env->ipr[IPR_PCBB];
env->ipr[IPR_ASN] = 0;
env->ipr[IPR_ASTEN] = 0;
env->ipr[IPR_ASTSR] = 0;
env->ipr[IPR_DATFX] = 0;
/* XXX: fix this */
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
env->ipr[IPR_FEN] = 0;
env->ipr[IPR_IPL] = 31;
env->ipr[IPR_MCES] = 0;
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
env->ipr[IPR_SISR] = 0;
env->ipr[IPR_VIRBND] = -1ULL;
}
#endif
qemu_init_vcpu(env);
return env;
}