mirror of https://github.com/xemu-project/xemu.git
target/arm: Inline scalar SUQADD and USQADD
This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
8f6343ae18
commit
1217edace8
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@ -274,14 +274,6 @@ DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64)
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DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32)
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DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64)
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DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32)
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DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32)
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@ -188,6 +188,38 @@ void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
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}
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/*
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* Set @res to the correctly saturated result.
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* Set @qc non-zero if saturation occured.
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*/
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void gen_suqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
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TCGv_i64 a, TCGv_i64 b, MemOp esz)
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{
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TCGv_i64 max = tcg_constant_i64((1ull << ((8 << esz) - 1)) - 1);
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_add_i64(t, a, b);
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tcg_gen_smin_i64(res, t, max);
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tcg_gen_xor_i64(t, t, res);
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tcg_gen_or_i64(qc, qc, t);
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}
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void gen_suqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b)
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{
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TCGv_i64 max = tcg_constant_i64(INT64_MAX);
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TCGv_i64 t = tcg_temp_new_i64();
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/* Maximum value that can be added to @a without overflow. */
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tcg_gen_sub_i64(t, max, a);
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/* Constrain addend so that the next addition never overflows. */
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tcg_gen_umin_i64(t, t, b);
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tcg_gen_add_i64(res, a, t);
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tcg_gen_xor_i64(t, t, b);
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tcg_gen_or_i64(qc, qc, t);
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}
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static void gen_suqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc,
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TCGv_vec a, TCGv_vec b)
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{
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@ -231,6 +263,7 @@ void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs,
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.write_aofs = true,
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.vece = MO_32 },
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{ .fniv = gen_suqadd_vec,
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.fni8 = gen_suqadd_d,
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.fno = gen_helper_gvec_suqadd_d,
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.opt_opc = vecop_list,
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.write_aofs = true,
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@ -242,6 +275,43 @@ void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs,
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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void gen_usqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
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TCGv_i64 a, TCGv_i64 b, MemOp esz)
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{
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TCGv_i64 max = tcg_constant_i64(MAKE_64BIT_MASK(0, 8 << esz));
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TCGv_i64 zero = tcg_constant_i64(0);
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_add_i64(tmp, a, b);
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tcg_gen_smin_i64(res, tmp, max);
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tcg_gen_smax_i64(res, res, zero);
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tcg_gen_xor_i64(tmp, tmp, res);
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tcg_gen_or_i64(qc, qc, tmp);
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}
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void gen_usqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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TCGv_i64 tneg = tcg_temp_new_i64();
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TCGv_i64 tpos = tcg_temp_new_i64();
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TCGv_i64 max = tcg_constant_i64(UINT64_MAX);
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TCGv_i64 zero = tcg_constant_i64(0);
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tcg_gen_add_i64(tmp, a, b);
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/* If @b is positive, saturate if (a + b) < a, aka unsigned overflow. */
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tcg_gen_movcond_i64(TCG_COND_LTU, tpos, tmp, a, max, tmp);
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/* If @b is negative, saturate if a < -b, ie subtraction is negative. */
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tcg_gen_neg_i64(tneg, b);
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tcg_gen_movcond_i64(TCG_COND_LTU, tneg, a, tneg, zero, tmp);
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/* Select correct result from sign of @b. */
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tcg_gen_movcond_i64(TCG_COND_LT, res, b, zero, tneg, tpos);
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tcg_gen_xor_i64(tmp, tmp, res);
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tcg_gen_or_i64(qc, qc, tmp);
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}
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static void gen_usqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc,
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TCGv_vec a, TCGv_vec b)
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{
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@ -288,6 +358,7 @@ void gen_gvec_usqadd_qc(unsigned vece, uint32_t rd_ofs,
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.write_aofs = true,
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.vece = MO_32 },
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{ .fniv = gen_usqadd_vec,
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.fni8 = gen_usqadd_d,
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.fno = gen_helper_gvec_usqadd_d,
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.opt_opc = vecop_list,
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.write_aofs = true,
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@ -236,171 +236,6 @@ uint64_t HELPER(neon_qadd_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
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return res;
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}
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/* Unsigned saturating accumulate of signed value
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*
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* Op1/Rn is treated as signed
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* Op2/Rd is treated as unsigned
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*
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* Explicit casting is used to ensure the correct sign extension of
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* inputs. The result is treated as a unsigned value and saturated as such.
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*
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* We use a macro for the 8/16 bit cases which expects signed integers of va,
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* vb, and vr for interim calculation and an unsigned 32 bit result value r.
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*/
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#define USATACC(bits, shift) \
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do { \
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va = sextract32(a, shift, bits); \
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vb = extract32(b, shift, bits); \
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vr = va + vb; \
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if (vr > UINT##bits##_MAX) { \
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SET_QC(); \
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vr = UINT##bits##_MAX; \
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} else if (vr < 0) { \
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SET_QC(); \
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vr = 0; \
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} \
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r = deposit32(r, shift, bits, vr); \
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} while (0)
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uint32_t HELPER(neon_uqadd_s8)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int16_t va, vb, vr;
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uint32_t r = 0;
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USATACC(8, 0);
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USATACC(8, 8);
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USATACC(8, 16);
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USATACC(8, 24);
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return r;
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}
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uint32_t HELPER(neon_uqadd_s16)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int32_t va, vb, vr;
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uint64_t r = 0;
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USATACC(16, 0);
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USATACC(16, 16);
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return r;
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}
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#undef USATACC
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uint32_t HELPER(neon_uqadd_s32)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int64_t va = (int32_t)a;
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int64_t vb = (uint32_t)b;
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int64_t vr = va + vb;
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if (vr > UINT32_MAX) {
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SET_QC();
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vr = UINT32_MAX;
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} else if (vr < 0) {
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SET_QC();
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vr = 0;
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}
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return vr;
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}
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uint64_t HELPER(neon_uqadd_s64)(CPUARMState *env, uint64_t a, uint64_t b)
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{
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uint64_t res;
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res = a + b;
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/* We only need to look at the pattern of SIGN bits to detect
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* +ve/-ve saturation
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*/
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if (~a & b & ~res & SIGNBIT64) {
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SET_QC();
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res = UINT64_MAX;
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} else if (a & ~b & res & SIGNBIT64) {
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SET_QC();
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res = 0;
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}
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return res;
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}
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/* Signed saturating accumulate of unsigned value
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*
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* Op1/Rn is treated as unsigned
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* Op2/Rd is treated as signed
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*
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* The result is treated as a signed value and saturated as such
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*
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* We use a macro for the 8/16 bit cases which expects signed integers of va,
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* vb, and vr for interim calculation and an unsigned 32 bit result value r.
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*/
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#define SSATACC(bits, shift) \
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do { \
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va = extract32(a, shift, bits); \
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vb = sextract32(b, shift, bits); \
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vr = va + vb; \
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if (vr > INT##bits##_MAX) { \
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SET_QC(); \
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vr = INT##bits##_MAX; \
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} else if (vr < INT##bits##_MIN) { \
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SET_QC(); \
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vr = INT##bits##_MIN; \
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} \
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r = deposit32(r, shift, bits, vr); \
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} while (0)
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uint32_t HELPER(neon_sqadd_u8)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int16_t va, vb, vr;
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uint32_t r = 0;
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SSATACC(8, 0);
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SSATACC(8, 8);
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SSATACC(8, 16);
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SSATACC(8, 24);
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return r;
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}
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uint32_t HELPER(neon_sqadd_u16)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int32_t va, vb, vr;
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uint32_t r = 0;
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SSATACC(16, 0);
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SSATACC(16, 16);
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return r;
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}
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#undef SSATACC
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uint32_t HELPER(neon_sqadd_u32)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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int64_t res;
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int64_t op1 = (uint32_t)a;
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int64_t op2 = (int32_t)b;
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res = op1 + op2;
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if (res > INT32_MAX) {
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SET_QC();
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res = INT32_MAX;
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} else if (res < INT32_MIN) {
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SET_QC();
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res = INT32_MIN;
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}
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return res;
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}
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uint64_t HELPER(neon_sqadd_u64)(CPUARMState *env, uint64_t a, uint64_t b)
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{
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uint64_t res;
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res = a + b;
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/* We only need to look at the pattern of SIGN bits to detect an overflow */
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if (((a & res)
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| (~b & res)
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| (a & ~b)) & SIGNBIT64) {
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SET_QC();
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res = INT64_MAX;
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}
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return res;
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}
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#define NEON_USAT(dest, src1, src2, type) do { \
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uint32_t tmp = (uint32_t)src1 - (uint32_t)src2; \
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if (tmp != (type)tmp) { \
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@ -9985,67 +9985,42 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
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static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
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bool is_q, unsigned size, int rn, int rd)
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{
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TCGv_i64 res, qc, a, b;
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if (!is_scalar) {
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gen_gvec_fn3(s, is_q, rd, rd, rn,
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is_u ? gen_gvec_usqadd_qc : gen_gvec_suqadd_qc, size);
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return;
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}
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if (size == 3) {
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TCGv_i64 tcg_rn = tcg_temp_new_i64();
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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res = tcg_temp_new_i64();
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qc = tcg_temp_new_i64();
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a = tcg_temp_new_i64();
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b = tcg_temp_new_i64();
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read_vec_element(s, tcg_rn, rn, 0, MO_64);
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read_vec_element(s, tcg_rd, rd, 0, MO_64);
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/* Read and extend scalar inputs to 64-bits. */
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read_vec_element(s, a, rd, 0, size | (is_u ? 0 : MO_SIGN));
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read_vec_element(s, b, rn, 0, size | (is_u ? MO_SIGN : 0));
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tcg_gen_ld_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc));
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if (is_u) { /* USQADD */
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gen_helper_neon_uqadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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} else { /* SUQADD */
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gen_helper_neon_sqadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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if (size == MO_64) {
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if (is_u) {
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gen_usqadd_d(res, qc, a, b);
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} else {
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gen_suqadd_d(res, qc, a, b);
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}
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write_vec_element(s, tcg_rd, rd, 0, MO_64);
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clear_vec_high(s, false, rd);
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} else {
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TCGv_i32 tcg_rn = tcg_temp_new_i32();
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_rn, rn, 0, size);
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read_vec_element_i32(s, tcg_rd, rd, 0, size);
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if (is_u) { /* USQADD */
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switch (size) {
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case 0:
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gen_helper_neon_uqadd_s8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_uqadd_s16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_uqadd_s32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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} else { /* SUQADD */
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switch (size) {
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case 0:
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gen_helper_neon_sqadd_u8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_sqadd_u16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_sqadd_u32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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if (is_u) {
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gen_usqadd_bhs(res, qc, a, b, size);
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} else {
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gen_suqadd_bhs(res, qc, a, b, size);
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/* Truncate signed 64-bit result for writeback. */
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tcg_gen_ext_i64(res, res, size);
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}
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write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
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write_vec_element_i32(s, tcg_rd, rd, 0, MO_32);
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clear_vec_high(s, false, rd);
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}
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write_fp_dreg(s, rd, res);
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tcg_gen_st_i64(qc, tcg_env, offsetof(CPUARMState, vfp.qc));
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}
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/* AdvSIMD scalar two reg misc
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@ -197,9 +197,17 @@ void gen_gvec_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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uint32_t a, uint32_t oprsz, uint32_t maxsz);
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void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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uint32_t a, uint32_t oprsz, uint32_t maxsz);
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||||
|
||||
void gen_suqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
|
||||
TCGv_i64 a, TCGv_i64 b, MemOp esz);
|
||||
void gen_suqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b);
|
||||
void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs,
|
||||
uint32_t rn_ofs, uint32_t rm_ofs,
|
||||
uint32_t opr_sz, uint32_t max_sz);
|
||||
|
||||
void gen_usqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
|
||||
TCGv_i64 a, TCGv_i64 b, MemOp esz);
|
||||
void gen_usqadd_d(TCGv_i64 res, TCGv_i64 qc, TCGv_i64 a, TCGv_i64 b);
|
||||
void gen_gvec_usqadd_qc(unsigned vece, uint32_t rd_ofs,
|
||||
uint32_t rn_ofs, uint32_t rm_ofs,
|
||||
uint32_t opr_sz, uint32_t max_sz);
|
||||
|
|
|
|||
Loading…
Reference in New Issue