mirror of https://github.com/xemu-project/xemu.git
target/sparc: Remove cpu_fpr[]
Use explicit loads and stores to env instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
52f46d4627
commit
1210a0367d
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@ -123,8 +123,7 @@ static TCGv cpu_gsr;
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#define cpu_xcc_C ({ qemu_build_not_reached(); NULL; })
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#endif
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/* Floating point registers */
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static TCGv_i64 cpu_fpr[TARGET_DPREGS];
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/* Floating point comparison registers */
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static TCGv_i32 cpu_fcc[TARGET_FCCREGS];
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#define env_field_offsetof(X) offsetof(CPUSPARCState, X)
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@ -209,50 +208,72 @@ static void gen_update_fprs_dirty(DisasContext *dc, int rd)
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}
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/* floating point registers moves */
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static int gen_offset_fpr_F(unsigned int reg)
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{
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int ret;
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tcg_debug_assert(reg < 32);
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ret= offsetof(CPUSPARCState, fpr[reg / 2]);
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if (reg & 1) {
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ret += offsetof(CPU_DoubleU, l.lower);
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} else {
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ret += offsetof(CPU_DoubleU, l.upper);
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}
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return ret;
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}
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static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
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{
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TCGv_i32 ret = tcg_temp_new_i32();
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if (src & 1) {
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tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
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} else {
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tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
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}
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tcg_gen_ld_i32(ret, tcg_env, gen_offset_fpr_F(src));
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return ret;
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}
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static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t, v);
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tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
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(dst & 1 ? 0 : 32), 32);
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tcg_gen_st_i32(v, tcg_env, gen_offset_fpr_F(dst));
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gen_update_fprs_dirty(dc, dst);
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}
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static int gen_offset_fpr_D(unsigned int reg)
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{
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tcg_debug_assert(reg < 64);
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tcg_debug_assert(reg % 2 == 0);
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return offsetof(CPUSPARCState, fpr[reg / 2]);
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}
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static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
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{
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return cpu_fpr[src / 2];
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TCGv_i64 ret = tcg_temp_new_i64();
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tcg_gen_ld_i64(ret, tcg_env, gen_offset_fpr_D(src));
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return ret;
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}
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static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
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{
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tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
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tcg_gen_st_i64(v, tcg_env, gen_offset_fpr_D(dst));
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gen_update_fprs_dirty(dc, dst);
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}
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static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src)
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{
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TCGv_i128 ret = tcg_temp_new_i128();
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TCGv_i64 h = gen_load_fpr_D(dc, src);
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TCGv_i64 l = gen_load_fpr_D(dc, src + 2);
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tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]);
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tcg_gen_concat_i64_i128(ret, l, h);
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return ret;
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}
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static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 v)
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{
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tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v);
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gen_update_fprs_dirty(dc, dst);
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TCGv_i64 h = tcg_temp_new_i64();
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TCGv_i64 l = tcg_temp_new_i64();
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tcg_gen_extr_i128_i64(l, h, v);
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gen_store_fpr_D(dc, dst, h);
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gen_store_fpr_D(dc, dst + 2, l);
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}
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/* moves */
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@ -1610,7 +1631,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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MemOp memop = da->memop;
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MemOp size = memop & MO_SIZE;
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TCGv_i32 d32;
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TCGv_i64 d64;
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TCGv_i64 d64, l64;
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TCGv addr_tmp;
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/* TODO: Use 128-bit load/store below. */
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@ -1632,16 +1653,20 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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break;
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case MO_64:
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop);
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d64 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
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gen_store_fpr_D(dc, rd, d64);
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break;
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case MO_128:
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d64 = tcg_temp_new_i64();
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l64 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
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addr_tmp = tcg_temp_new();
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tcg_gen_addi_tl(addr_tmp, addr, 8);
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
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tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
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tcg_gen_qemu_ld_i64(l64, addr_tmp, da->mem_idx, memop);
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gen_store_fpr_D(dc, rd, d64);
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gen_store_fpr_D(dc, rd + 2, l64);
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break;
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default:
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g_assert_not_reached();
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@ -1653,9 +1678,11 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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if (orig_size == MO_64 && (rd & 7) == 0) {
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/* The first operation checks required alignment. */
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addr_tmp = tcg_temp_new();
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d64 = tcg_temp_new_i64();
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for (int i = 0; ; ++i) {
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
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tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx,
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memop | (i == 0 ? MO_ALIGN_64 : 0));
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gen_store_fpr_D(dc, rd + 2 * i, d64);
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if (i == 7) {
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break;
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}
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@ -1670,8 +1697,9 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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case GET_ASI_SHORT:
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/* Valid for lddfa only. */
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if (orig_size == MO_64) {
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN);
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d64 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop | MO_ALIGN);
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gen_store_fpr_D(dc, rd, d64);
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} else {
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gen_exception(dc, TT_ILL_INSN);
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}
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@ -1696,17 +1724,19 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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gen_store_fpr_F(dc, rd, d32);
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break;
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case MO_64:
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gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr,
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r_asi, r_mop);
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d64 = tcg_temp_new_i64();
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gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
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gen_store_fpr_D(dc, rd, d64);
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break;
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case MO_128:
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d64 = tcg_temp_new_i64();
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l64 = tcg_temp_new_i64();
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gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
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addr_tmp = tcg_temp_new();
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tcg_gen_addi_tl(addr_tmp, addr, 8);
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gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp,
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r_asi, r_mop);
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tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
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gen_helper_ld_asi(l64, tcg_env, addr_tmp, r_asi, r_mop);
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gen_store_fpr_D(dc, rd, d64);
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gen_store_fpr_D(dc, rd + 2, l64);
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break;
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default:
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g_assert_not_reached();
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@ -1722,6 +1752,7 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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MemOp memop = da->memop;
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MemOp size = memop & MO_SIZE;
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TCGv_i32 d32;
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TCGv_i64 d64;
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TCGv addr_tmp;
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/* TODO: Use 128-bit load/store below. */
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@ -1741,8 +1772,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN);
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break;
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case MO_64:
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN_4);
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d64 = gen_load_fpr_D(dc, rd);
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tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_4);
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break;
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case MO_128:
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/* Only 4-byte alignment required. However, it is legal for the
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@ -1750,11 +1781,12 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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required to fix it up. Requiring 16-byte alignment here avoids
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having to probe the second page before performing the first
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write. */
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN_16);
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d64 = gen_load_fpr_D(dc, rd);
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tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_16);
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addr_tmp = tcg_temp_new();
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tcg_gen_addi_tl(addr_tmp, addr, 8);
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
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d64 = gen_load_fpr_D(dc, rd + 2);
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tcg_gen_qemu_st_i64(d64, addr_tmp, da->mem_idx, memop);
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break;
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default:
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g_assert_not_reached();
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@ -1767,7 +1799,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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/* The first operation checks required alignment. */
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addr_tmp = tcg_temp_new();
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for (int i = 0; ; ++i) {
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
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d64 = gen_load_fpr_D(dc, rd + 2 * i);
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tcg_gen_qemu_st_i64(d64, addr, da->mem_idx,
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memop | (i == 0 ? MO_ALIGN_64 : 0));
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if (i == 7) {
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break;
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@ -1783,8 +1816,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
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case GET_ASI_SHORT:
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/* Valid for stdfa only. */
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if (orig_size == MO_64) {
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN);
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d64 = gen_load_fpr_D(dc, rd);
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tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN);
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} else {
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gen_exception(dc, TT_ILL_INSN);
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}
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@ -2029,13 +2062,17 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
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{
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#ifdef TARGET_SPARC64
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TCGv c2 = tcg_constant_tl(cmp->c2);
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TCGv_i64 h = tcg_temp_new_i64();
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TCGv_i64 l = tcg_temp_new_i64();
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tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2], cmp->c1, c2,
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cpu_fpr[rs / 2], cpu_fpr[rd / 2]);
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tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2 + 1], cmp->c1, c2,
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cpu_fpr[rs / 2 + 1], cpu_fpr[rd / 2 + 1]);
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gen_update_fprs_dirty(dc, rd);
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tcg_gen_movcond_i64(cmp->cond, h, cmp->c1, c2,
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gen_load_fpr_D(dc, rs),
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gen_load_fpr_D(dc, rd));
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tcg_gen_movcond_i64(cmp->cond, l, cmp->c1, c2,
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gen_load_fpr_D(dc, rs + 2),
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gen_load_fpr_D(dc, rd + 2));
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gen_store_fpr_D(dc, rd, h);
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gen_store_fpr_D(dc, rd + 2, l);
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#else
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qemu_build_not_reached();
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#endif
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@ -4211,39 +4248,24 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)
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TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL)
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TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ)
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static bool do_fc(DisasContext *dc, int rd, bool c)
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static bool do_fc(DisasContext *dc, int rd, int32_t c)
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{
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uint64_t mask;
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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if (rd & 1) {
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mask = MAKE_64BIT_MASK(0, 32);
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} else {
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mask = MAKE_64BIT_MASK(32, 32);
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}
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if (c) {
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tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask);
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} else {
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tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask);
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}
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gen_update_fprs_dirty(dc, rd);
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gen_store_fpr_F(dc, rd, tcg_constant_i32(c));
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return advance_pc(dc);
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}
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TRANS(FZEROs, VIS1, do_fc, a->rd, 0)
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TRANS(FONEs, VIS1, do_fc, a->rd, 1)
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TRANS(FONEs, VIS1, do_fc, a->rd, -1)
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static bool do_dc(DisasContext *dc, int rd, int64_t c)
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{
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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tcg_gen_movi_i64(cpu_fpr[rd / 2], c);
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gen_update_fprs_dirty(dc, rd);
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gen_store_fpr_D(dc, rd, tcg_constant_i64(c));
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return advance_pc(dc);
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}
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@ -5137,12 +5159,6 @@ void sparc_tcg_init(void)
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
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};
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static const char fregnames[32][4] = {
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"f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
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"f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
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"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
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"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
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};
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static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
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#ifdef TARGET_SPARC64
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@ -5199,12 +5215,6 @@ void sparc_tcg_init(void)
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(i - 8) * sizeof(target_ulong),
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gregnames[i]);
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}
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for (i = 0; i < TARGET_DPREGS; i++) {
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cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env,
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offsetof(CPUSPARCState, fpr[i]),
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fregnames[i]);
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}
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}
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void sparc_restore_state_to_opc(CPUState *cs,
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