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target/xtensa updates for v7.1: 

- expand test coverage to MMUv3, cores without windowed registers or
   loop option;
 - import lx106 core (used in the esp8266 IoT chips);
 - use tcg_constant_* in the front end;
 - add clock input to the xtensa CPU;
 - fix reset state of the xtensa MX PIC;
 - implement cache testing opcodes.
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Merge tag '20220506-xtensa-1' of https://github.com/OSLL/qemu-xtensa into staging

target/xtensa updates for v7.1:

- expand test coverage to MMUv3, cores without windowed registers or
  loop option;
- import lx106 core (used in the esp8266 IoT chips);
- use tcg_constant_* in the front end;
- add clock input to the xtensa CPU;
- fix reset state of the xtensa MX PIC;
- implement cache testing opcodes.

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# gpg: Signature made Fri 06 May 2022 05:40:26 PM CDT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [undefined]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* tag '20220506-xtensa-1' of https://github.com/OSLL/qemu-xtensa:
  target/xtensa: implement cache test option opcodes
  tests/tcg/xtensa: fix vectors and checks in timer test
  tests/tcg/xtensa: enable mmu tests for MMUv3
  tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
  tests/tcg/xtensa: remove dependency on the loop option
  tests/tcg/xtensa: fix watchpoint test
  tests/tcg/xtensa: restore vecbase SR after test
  tests/tcg/xtensa: fix build for cores without windowed registers
  hw/xtensa: fix reset value of MIROUT register of MX PIC
  target/xtensa: add clock input to xtensa CPU
  target/xtensa: import core lx106
  target/xtensa: use tcg_constant_* for remaining opcodes
  target/xtensa: use tcg_constant_* for FPU conversion opcodes
  target/xtensa: use tcg_constant_* for numbered special registers
  target/xtensa: use tcg_constant_* for TLB opcodes
  target/xtensa: use tcg_constant_* for exceptions
  target/xtensa: use tcg_contatnt_* for numeric literals
  target/xtensa: fix missing tcg_temp_free in gen_window_check

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 21:37:46 -05:00
parent 13220a46e2 59491e97f8
commit 11314643c3
16 changed files with 8604 additions and 259 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/xtensa/mx_pic.c
View File

@ -334,7 +334,7 @@ void xtensa_mx_pic_reset(void *opaque)
mx->miasg = 0;
mx->mipipart = 0;
for (i = 0; i < mx->n_irq; ++i) {
mx->mirout[i] = 1;
mx->mirout[i] = 0;
}
for (i = 0; i < mx->n_cpu; ++i) {
mx->cpu[i].mipicause = 0;

51
target/xtensa/core-lx106.c Normal file
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@ -0,0 +1,51 @@
/*
* Copyright (c) 2022, Simon Safar, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"
#include "qemu/host-utils.h"
#include "core-lx106/core-isa.h"
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_lx106
#include "core-lx106/xtensa-modules.c.inc"
static XtensaConfig lx106 __attribute__((unused)) = {
.name = "lx106",
.gdb_regmap = {
.reg = {
#include "core-lx106/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
.clock_freq_khz = 40000,
DEFAULT_SECTIONS
};
REGISTER_CORE(lx106)

470
target/xtensa/core-lx106/core-isa.h Normal file
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@ -0,0 +1,470 @@
/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Copyright (c) 1999-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 0 /* windowed registers option */
#define XCHAL_NUM_AREGS 16 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 4 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 0 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_FP 0 /* floating point pkg */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 1 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 800001 /* sw version of this header */
#define XCHAL_CORE_ID "lx106" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC28CDAFA /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1082B6F6 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 230001 /* major*100+minor */
#define XCHAL_HW_REL_LX3 1
#define XCHAL_HW_REL_LX3_0 1
#define XCHAL_HW_REL_LX3_0_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instruction ROM 0: */
#define XCHAL_INSTROM0_VADDR 0x40200000
#define XCHAL_INSTROM0_PADDR 0x40200000
// #define XCHAL_INSTROM0_VADDR 0x400000
// #define XCHAL_INSTROM0_PADDR 0x400000
#define XCHAL_INSTROM0_SIZE 1048576
#define XCHAL_INSTROM0_ECC_PARITY 0
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000
#define XCHAL_INSTRAM0_PADDR 0x40000000
#define XCHAL_INSTRAM0_SIZE 1048576
#define XCHAL_INSTRAM0_ECC_PARITY 0
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x40100000
#define XCHAL_INSTRAM1_PADDR 0x40100000
#define XCHAL_INSTRAM1_SIZE 1048576
#define XCHAL_INSTRAM1_ECC_PARITY 0
/* Data ROM 0: */
#define XCHAL_DATAROM0_VADDR 0x3FF40000
#define XCHAL_DATAROM0_PADDR 0x3FF40000
#define XCHAL_DATAROM0_SIZE 262144
#define XCHAL_DATAROM0_ECC_PARITY 0
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3FFC0000
#define XCHAL_DATARAM0_PADDR 0x3FFC0000
#define XCHAL_DATARAM0_SIZE 262144
#define XCHAL_DATARAM0_ECC_PARITY 0
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x3FF80000
#define XCHAL_DATARAM1_PADDR 0x3FF80000
#define XCHAL_DATARAM1_SIZE 262144
#define XCHAL_DATARAM1_ECC_PARITY 0
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0x3FF00000
#define XCHAL_XLMI0_PADDR 0x3FF00000
#define XCHAL_XLMI0_SIZE 262144
#define XCHAL_XLMI0_ECC_PARITY 0
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 13 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x00003FFF
#define XCHAL_INTLEVEL2_MASK 0x00000000
#define XCHAL_INTLEVEL3_MASK 0x00004000
#define XCHAL_INTLEVEL4_MASK 0x00000000
#define XCHAL_INTLEVEL5_MASK 0x00000000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00000000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00003FFF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00003FFF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00007FFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00007FFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00007FFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 1
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 3
#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 3 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00003F00
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000003F
#define XCHAL_INTTYPE_MASK_TIMER 0x00000040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL3_NUM 14
/* (There are many interrupts each at level(s) 1.) */
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 11 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT12_NUM 14 /* (intlevel 3) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000080
#define XCHAL_RESET_VECTOR1_PADDR 0x40000080
#define XCHAL_RESET_VECTOR_VADDR 0x50000000
#define XCHAL_RESET_VECTOR_PADDR 0x50000000
// #define XCHAL_RESET_VECTOR0_VADDR 0x4000f8
// #define XCHAL_RESET_VECTOR0_PADDR 0x4000f8
// #define XCHAL_RESET_VECTOR1_VADDR 0x40000080
// #define XCHAL_RESET_VECTOR1_PADDR 0x40000080
// #define XCHAL_RESET_VECTOR_VADDR 0x4000f8
// #define XCHAL_RESET_VECTOR_PADDR 0x4000f8
#define XCHAL_USER_VECOFS 0x00000050
#define XCHAL_USER_VECTOR_VADDR 0x40000050
#define XCHAL_USER_VECTOR_PADDR 0x40000050
#define XCHAL_KERNEL_VECOFS 0x00000030
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000030
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000030
#define XCHAL_DOUBLEEXC_VECOFS 0x00000070
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x40000070
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x40000070
#define XCHAL_INTLEVEL2_VECOFS 0x00000010
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000010
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000010
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x00000020
#define XCHAL_NMI_VECTOR_VADDR 0x40000020
#define XCHAL_NMI_VECTOR_PADDR 0x40000020
#define XCHAL_INTLEVEL3_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL3_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL3_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 1 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 1 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

83
target/xtensa/core-lx106/gdb-config.c.inc Normal file
View File

@ -0,0 +1,83 @@
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Copyright (c) 2003-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
XTREG( 0, 0,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 17, 68, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
XTREG( 21, 84, 6, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
XTREG( 23, 92, 1, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 32,128, 6, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 33,132, 6, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG( 36,144,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
XTREG( 37,148,15, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG( 38,152,15, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG( 39,156,15, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG( 40,160,15, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG( 42,168, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG( 43,172,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG( 44,176,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG( 46,184,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG( 47,188, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG( 48,192,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG( 49,196,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG( 50,200, 4, 4, 4,0x2002,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask0,0,0,0)
XTREG( 51,204, 1, 4, 4,0x2003,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask1,0,0,0)
XTREG( 52,208, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask2,0,0,0)
XTREG( 53,212,20, 4, 4,0x2005,0x0006,-2, 6,0x1010,litbaddr,
0,0,&xtensa_mask3,0,0,0)
XTREG( 54,216, 1, 4, 4,0x2006,0x0006,-2, 6,0x1010,litben,
0,0,&xtensa_mask4,0,0,0)
XTREG_END

7668
target/xtensa/core-lx106/xtensa-modules.c.inc Normal file
View File

File diff suppressed because it is too large Load Diff

1
target/xtensa/cores.list
View File

@ -4,6 +4,7 @@ core-de212.c
core-de233_fpu.c
core-dsp3400.c
core-fsf.c
core-lx106.c
core-sample_controller.c
core-test_kc705_be.c
core-test_mmuhifi_c3.c

15
target/xtensa/cpu.c
View File

@ -34,6 +34,7 @@
#include "fpu/softfloat.h"
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "hw/qdev-clock.h"
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
@ -172,9 +173,23 @@ static void xtensa_cpu_initfn(Object *obj)
memory_region_init_io(env->system_er, obj, NULL, env, "er",
UINT64_C(0x100000000));
address_space_init(env->address_space_er, env->system_er, "ER");
cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
#endif
}
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
{
DeviceState *cpu;
cpu = DEVICE(object_new(cpu_type));
qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
qdev_realize(cpu, NULL, &error_abort);
return XTENSA_CPU(cpu);
}
#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",

5
target/xtensa/cpu.h
View File

@ -31,6 +31,7 @@
#include "cpu-qom.h"
#include "qemu/cpu-float.h"
#include "exec/cpu-defs.h"
#include "hw/clock.h"
#include "xtensa-isa.h"
/* Xtensa processors have a weak memory model */
@ -559,6 +560,7 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
Clock *clock;
CPUNegativeOffsetState neg;
CPUXtensaState env;
};
@ -793,4 +795,7 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
}
}
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
Clock *cpu_refclk);
#endif

7
target/xtensa/op_helper.c
View File

@ -38,12 +38,12 @@
void HELPER(update_ccount)(CPUXtensaState *env)
{
XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
env->ccount_time = now;
env->sregs[CCOUNT] = env->ccount_base +
(uint32_t)((now - env->time_base) *
env->config->clock_freq_khz / 1000000);
(uint32_t)clock_ns_to_ticks(cpu->clock, now - env->time_base);
}
void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
@ -59,6 +59,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v)
void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
{
XtensaCPU *cpu = XTENSA_CPU(env_cpu(env));
uint64_t dcc;
qatomic_and(&env->sregs[INTSET],
@ -66,7 +67,7 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i)
HELPER(update_ccount)(env);
dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1;
timer_mod(env->ccompare[i].timer,
env->ccount_time + (dcc * 1000000) / env->config->clock_freq_khz);
env->ccount_time + clock_ticks_to_ns(cpu->clock, dcc));
env->yield_needed = 1;
}

211
target/xtensa/translate.c
View File

@ -306,32 +306,25 @@ static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
TCGv_i32 tmp = tcg_const_i32(32);
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
tcg_temp_free(tmp);
}
static void gen_exception(DisasContext *dc, int excp)
{
TCGv_i32 tmp = tcg_const_i32(excp);
gen_helper_exception(cpu_env, tmp);
tcg_temp_free(tmp);
gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
TCGv_i32 tcause = tcg_const_i32(cause);
gen_helper_exception_cause(cpu_env, tpc, tcause);
tcg_temp_free(tpc);
tcg_temp_free(tcause);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
@ -340,11 +333,8 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause)
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
TCGv_i32 tcause = tcg_const_i32(cause);
gen_helper_debug_exception(cpu_env, tpc, tcause);
tcg_temp_free(tpc);
tcg_temp_free(tcause);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
@ -406,19 +396,15 @@ static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
TCGv_i32 tmp = tcg_const_i32(dest);
gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
tcg_temp_free(tmp);
gen_jump_slot(dc, tcg_constant_i32(dest),
adjust_jump_slot(dc, dest, slot));
}
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
TCGv_i32 tcallinc = tcg_const_i32(callinc);
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_temp_free(tcallinc);
tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fffffff));
gen_jump_slot(dc, dest, slot);
@ -464,9 +450,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
TCGv_i32 tmp = tcg_const_i32(t1);
gen_brcond(dc, cond, t0, tmp, addr);
tcg_temp_free(tmp);
gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@ -551,28 +535,13 @@ static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop,
return mop;
}
#ifndef CONFIG_USER_ONLY
static void gen_waiti(DisasContext *dc, uint32_t imm4)
{
TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
TCGv_i32 intlevel = tcg_const_i32(imm4);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_waiti(cpu_env, pc, intlevel);
tcg_temp_free(pc);
tcg_temp_free(intlevel);
}
#endif
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
if (r / 4 > dc->window) {
TCGv_i32 pc = tcg_const_i32(dc->pc);
TCGv_i32 w = tcg_const_i32(r / 4);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
@ -1080,17 +1049,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
}
if (op_flags & XTENSA_OP_UNDERFLOW) {
TCGv_i32 tmp = tcg_const_i32(dc->pc);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_test_underflow_retw(cpu_env, tmp);
tcg_temp_free(tmp);
gen_helper_test_underflow_retw(cpu_env, pc);
}
if (op_flags & XTENSA_OP_ALLOCA) {
TCGv_i32 tmp = tcg_const_i32(dc->pc);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_movsp(cpu_env, tmp);
tcg_temp_free(tmp);
gen_helper_movsp(cpu_env, pc);
}
if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
@ -1670,13 +1637,10 @@ static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[],
static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 pc = tcg_const_i32(dc->pc);
TCGv_i32 s = tcg_const_i32(arg[0].imm);
TCGv_i32 imm = tcg_const_i32(arg[1].imm);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_constant_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
tcg_temp_free(imm);
tcg_temp_free(s);
tcg_temp_free(pc);
}
static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
@ -1718,10 +1682,9 @@ static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_const_i32(par[0]);
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_itlb(cpu_env, arg[0].in, dtlb);
tcg_temp_free(dtlb);
#endif
}
@ -1757,12 +1720,10 @@ static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 tpc = tcg_const_i32(dc->pc);
TCGv_i32 write = tcg_const_i32(is_write);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_check_exclusive(cpu_env, tpc, addr, write);
tcg_temp_free(tpc);
tcg_temp_free(write);
gen_helper_check_exclusive(cpu_env, pc, addr,
tcg_constant_i32(is_write));
}
}
#endif
@ -1805,6 +1766,12 @@ static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],
tcg_temp_free(addr);
}
static void translate_lct(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
tcg_gen_movi_i32(arg[0].out, 0);
}
static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@ -1957,11 +1924,10 @@ static void translate_mov(DisasContext *dc, const OpcodeArg arg[],
static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero, arg[1].in, arg[0].in);
tcg_temp_free(zero);
}
static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
@ -1973,7 +1939,7 @@ static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@ -1981,7 +1947,6 @@ static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
tcg_temp_free(zero);
}
static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
@ -2060,11 +2025,10 @@ static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_const_i32(par[0]);
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
tcg_temp_free(dtlb);
#endif
}
@ -2142,10 +2106,9 @@ static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[],
"Illegal retw instruction(pc = %08x)\n", dc->pc);
return XTENSA_OP_ILL;
} else {
TCGv_i32 tmp = tcg_const_i32(dc->pc);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_test_ill_retw(cpu_env, tmp);
tcg_temp_free(tmp);
gen_helper_test_ill_retw(cpu_env, pc);
return 0;
}
}
@ -2263,10 +2226,9 @@ static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
gen_helper_rtlb0,
gen_helper_rtlb1,
};
TCGv_i32 dtlb = tcg_const_i32(par[0]);
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
tcg_temp_free(dtlb);
#endif
}
@ -2306,10 +2268,9 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
#else
static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
{
TCGv_i32 tpc = tcg_const_i32(dc->pc);
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_check_atomctl(cpu_env, tpc, addr);
tcg_temp_free(tpc);
gen_helper_check_atomctl(cpu_env, pc, addr);
}
#endif
@ -2530,9 +2491,7 @@ static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],
static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
gen_right_shift_sar(dc, tmp);
tcg_temp_free(tmp);
gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm));
}
static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
@ -2566,7 +2525,12 @@ static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
gen_waiti(dc, arg[0].imm);
TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
#endif
}
@ -2574,10 +2538,9 @@ static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
TCGv_i32 dtlb = tcg_const_i32(par[0]);
TCGv_i32 dtlb = tcg_constant_i32(par[0]);
gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
tcg_temp_free(dtlb);
#endif
}
@ -2629,15 +2592,13 @@ static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
uint32_t id = par[0] - CCOMPARE;
TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
gen_helper_update_ccompare(cpu_env, tmp);
tcg_temp_free(tmp);
gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
#endif
}
@ -2657,11 +2618,9 @@ static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKA;
TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
tcg_temp_free(tmp);
gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@ -2670,11 +2629,9 @@ static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - DBREAKC;
TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
tcg_temp_free(tmp);
gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@ -2683,11 +2640,9 @@ static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
{
#ifndef CONFIG_USER_ONLY
unsigned id = par[0] - IBREAKA;
TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
tcg_temp_free(tmp);
gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
#endif
}
@ -3370,6 +3325,14 @@ static const XtensaOpcodeOps core_ops[] = {
.translate = translate_ldst,
.par = (const uint32_t[]){MO_UB, false, false},
.op_flags = XTENSA_OP_LOAD,
}, {
.name = "ldct",
.translate = translate_lct,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "ldcw",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "lddec",
.translate = translate_mac16,
@ -3383,6 +3346,14 @@ static const XtensaOpcodeOps core_ops[] = {
}, {
.name = "ldpte",
.op_flags = XTENSA_OP_ILL,
}, {
.name = "lict",
.translate = translate_lct,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "licw",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = (const char * const[]) {
"loop", "loop.w15", NULL,
@ -4686,12 +4657,28 @@ static const XtensaOpcodeOps core_ops[] = {
.name = "saltu",
.translate = translate_salt,
.par = (const uint32_t[]){TCG_COND_LTU},
}, {
.name = "sdct",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "sdcw",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "setb_expstate",
.translate = translate_setb_expstate,
}, {
.name = "sext",
.translate = translate_sext,
}, {
.name = "sict",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "sicw",
.translate = translate_nop,
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
.name = "simcall",
.translate = translate_simcall,
@ -6444,7 +6431,7 @@ static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
[COMPARE_OLE] = gen_helper_ole_d,
[COMPARE_ULE] = gen_helper_ule_d,
};
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@ -6456,7 +6443,6 @@ static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movcond_i32(TCG_COND_NE,
arg[0].out, res, zero,
set_br, clr_br);
tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@ -6476,7 +6462,7 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
[COMPARE_ULE] = gen_helper_ule_s,
};
OpcodeArg arg32[3];
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 res = tcg_temp_new_i32();
TCGv_i32 set_br = tcg_temp_new_i32();
TCGv_i32 clr_br = tcg_temp_new_i32();
@ -6490,7 +6476,6 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, res, zero,
set_br, clr_br);
put_f32_i2(arg, arg32, 1, 2);
tcg_temp_free(zero);
tcg_temp_free(res);
tcg_temp_free(set_br);
tcg_temp_free(clr_br);
@ -6539,20 +6524,19 @@ static void translate_const_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
if (par[0]) {
gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
} else {
gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
}
tcg_temp_free(scale);
}
static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
TCGv_i32 scale = tcg_constant_i32(-arg[2].imm);
OpcodeArg arg32[1];
get_f32_o1(arg, arg32, 0);
@ -6562,14 +6546,13 @@ static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
}
put_f32_o1(arg, arg32, 0);
tcg_temp_free(scale);
}
static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
TCGv_i32 scale = tcg_const_i32(arg[2].imm);
TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
if (par[1]) {
gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
@ -6578,15 +6561,13 @@ static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
rounding_mode, scale);
}
tcg_temp_free(rounding_mode);
tcg_temp_free(scale);
}
static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
TCGv_i32 scale = tcg_const_i32(arg[2].imm);
TCGv_i32 rounding_mode = tcg_constant_i32(par[0]);
TCGv_i32 scale = tcg_constant_i32(arg[2].imm);
OpcodeArg arg32[2];
get_f32_i1(arg, arg32, 1);
@ -6598,8 +6579,6 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
rounding_mode, scale);
}
put_f32_i1(arg, arg32, 1);
tcg_temp_free(rounding_mode);
tcg_temp_free(scale);
}
static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
@ -6666,14 +6645,13 @@ static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i64 zero = tcg_const_i64(0);
TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i64 arg2 = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(arg2, arg[2].in);
tcg_gen_movcond_i64(par[0], arg[0].out,
arg2, zero,
arg[1].in, arg[0].in);
tcg_temp_free_i64(zero);
tcg_temp_free_i64(arg2);
}
@ -6681,12 +6659,11 @@ static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_movcond_i32(par[0], arg[0].out,
arg[2].in, zero,
arg[1].in, arg[0].in);
tcg_temp_free(zero);
} else {
translate_movcond_d(dc, arg, par);
}
@ -6695,7 +6672,7 @@ static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i64 zero = tcg_const_i64(0);
TCGv_i64 zero = tcg_constant_i64(0);
TCGv_i32 tmp1 = tcg_temp_new_i32();
TCGv_i64 tmp2 = tcg_temp_new_i64();
@ -6704,7 +6681,6 @@ static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
tcg_gen_movcond_i64(par[0],
arg[0].out, tmp2, zero,
arg[1].in, arg[0].in);
tcg_temp_free_i64(zero);
tcg_temp_free_i32(tmp1);
tcg_temp_free_i64(tmp2);
}
@ -6713,7 +6689,7 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
if (arg[0].num_bits == 32) {
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
@ -6721,7 +6697,6 @@ static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
arg[0].out, tmp, zero,
arg[1].in, arg[0].in);
tcg_temp_free(tmp);
tcg_temp_free(zero);
} else {
translate_movp_d(dc, arg, par);
}

2
tests/tcg/xtensa/crt.S
View File

@ -8,10 +8,12 @@
.text
.global _start
_start:
#if XCHAL_HAVE_WINDOWED
movi a2, 1
wsr a2, windowstart
movi a2, 0
wsr a2, windowbase
#endif
movi a1, _fstack
movi a2, 0x4000f
wsr a2, ps

86
tests/tcg/xtensa/test_break.S
View File

@ -200,64 +200,70 @@ test_end
.endm
#if XCHAL_NUM_DBREAK
#define DB0 0
#if XCHAL_NUM_DBREAK > 1
#define DB1 1
#else
#define DB1 0
#endif
test dbreak_exact
dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
dbreak_test DB0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
dbreak_test DB1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
test_end
test dbreak_overlap
dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
test DBdbreak_overlap
dbreak_test DB0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
dbreak_test DB1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
dbreak_test DB0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
dbreak_test DB1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i
dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
dbreak_test DB1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007c, l32i
dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i
dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
dbreak_test DB0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000078, l32i
dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i
dbreak_test DB0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
dbreak_test DB1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
dbreak_test DB0, 0x40000020, 0xd0000060, 0xd0000074, l32i
dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
dbreak_test DB0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
dbreak_test DB1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
dbreak_test DB1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
dbreak_test DB0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i
dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i
dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i
dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007b, s8i
dbreak_test DB1, 0x80000038, 0xd0000078, 0xd000007a, s16i
dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007c, s32i
dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i
dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i
dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i
dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000075, s8i
dbreak_test DB0, 0x80000030, 0xd0000070, 0xd0000076, s16i
dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000078, s32i
dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i
dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i
dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i
dbreak_test DB0, 0x80000020, 0xd0000060, 0xd000006f, s8i
dbreak_test DB1, 0x80000020, 0xd0000060, 0xd0000070, s16i
dbreak_test DB0, 0x80000020, 0xd0000060, 0xd0000074, s32i
test_end
test dbreak_invalid
dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test DBdbreak_invalid
dbreak_test DB0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
dbreak_test DB1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test_end
#endif

182
tests/tcg/xtensa/test_mmu.S
View File

@ -2,7 +2,9 @@
test_suite mmu
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_HAVE_PTP_MMU
#define BASE 0x20000000
#define TLB_BASE 0x80000000
.purgem test_init
@ -29,17 +31,27 @@ test_suite mmu
idtlb a2
movi a2, 0x00000009
idtlb a2
#if XCHAL_HAVE_SPANNING_WAY
movi a2, BASE | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
movi a2, TLB_BASE | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
movi a2, TLB_BASE
wsr a2, ptevaddr
#endif
.endm
test tlb_group
movi a2, 0x04000002 /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
witlb a2, a3
movi a3, 0x00200004
rdtlb0 a1, a3
ritlb0 a2, a3
movi a3, 0x01000001
movi a3, BASE + 0x01000001
assert eq, a1, a3
assert eq, a2, a3
movi a3, 0x00200004
@ -48,17 +60,17 @@ test tlb_group
movi a3, 0x04000002
assert eq, a1, a3
assert eq, a2, a3
movi a3, 0x01234567
movi a3, BASE + 0x01234567
pdtlb a1, a3
pitlb a2, a3
movi a3, 0x01234014
movi a3, BASE + 0x01234014
assert eq, a1, a3
movi a3, 0x0123400c
movi a3, BASE + 0x0123400c
assert eq, a2, a3
movi a3, 0x00200004
idtlb a3
iitlb a3
movi a3, 0x01234567
movi a3, BASE + 0x01234567
pdtlb a1, a3
pitlb a2, a3
movi a3, 0x00000010
@ -72,7 +84,7 @@ test_end
test itlb_miss
set_vector kernel, 1f
movi a3, 0x00100000
movi a3, BASE + 0x00100000
jx a3
test_fail
1:
@ -86,7 +98,7 @@ test_end
test dtlb_miss
set_vector kernel, 1f
movi a3, 0x00100000
movi a3, BASE + 0x00100000
l8ui a2, a3, 0
test_fail
1:
@ -116,11 +128,11 @@ test dtlb_multi_hit
set_vector kernel, 1f
movi a2, 0x04000002 /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
movi a3, 0x01200007 /* VPN */
movi a3, BASE + 0x01200007 /* VPN */
wdtlb a2, a3
movi a3, 0x01200000
movi a3, BASE + 0x01200000
pdtlb a2, a3
test_fail
1:
@ -168,15 +180,18 @@ test load_store_privilege
and a3, a3, a1
movi a1, 4
or a3, a3, a1
movi a5, BASE
add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
add a1, a1, a5
movi a2, 0x04000003 /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
movi a3, 0x01200001
movi a3, BASE + 0x01200001
movi a2, 0x4004f
jx a1
10:
@ -192,6 +207,7 @@ test load_store_privilege
movi a3, 1b
movi a1, 0x000fffff
and a3, a3, a1
add a3, a3, a5
assert eq, a2, a3
rsr a2, exccause
movi a3, 26
@ -206,9 +222,9 @@ test cring_load_store_privilege
set_vector double, 2f
movi a2, 0x04000003 /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
movi a3, 0x01200004
movi a3, BASE + 0x01200004
movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
wsr a2, ps
isync
@ -245,10 +261,13 @@ test inst_fetch_prohibited
and a3, a3, a1
movi a1, 4
or a3, a3, a1
movi a5, BASE
add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
add a1, a1, a5
jx a1
.align 4
10:
@ -268,9 +287,9 @@ test load_prohibited
set_vector kernel, 2f
movi a2, 0x0400000c /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
movi a3, 0x01200002
movi a3, BASE + 0x01200002
1:
l8ui a2, a3, 0
test_fail
@ -289,9 +308,9 @@ test store_prohibited
set_vector kernel, 2f
movi a2, 0x04000001 /* PPN */
movi a3, 0x01200004 /* VPN */
movi a3, BASE + 0x01200004 /* VPN */
wdtlb a2, a3
movi a3, 0x01200003
movi a3, BASE + 0x01200003
l8ui a2, a3, 0
1:
s8i a2, a3, 0
@ -311,10 +330,10 @@ test_end
* and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr
*/
.macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr
movi a2, 0x80000000
movi a2, TLB_BASE
wsr a2, ptevaddr
movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */
wdtlb a4, a3
isync
@ -324,7 +343,7 @@ test_end
add a2, a1, a2
s32i a3, a2, 0
movi a3, 0x80000007 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */
wdtlb a4, a3
isync
@ -343,10 +362,13 @@ test_end
and a3, a3, a1
movi a1, 4
or a3, a3, a1
movi a5, BASE
add a3, a3, a5
witlb a2, a3
movi a3, 10f
movi a1, 0x000fffff
and a1, a3, a1
add a1, a1, a5
movi a2, 0
wsr a2, excvaddr
@ -396,6 +418,8 @@ test_end
movi a2, (\vaddr)
movi a1, 0xfffff
and a1, a1, a2
movi a5, BASE
add a1, a1, a5
rsr a2, epc1
assert eq, a1, a2
.endm
@ -403,7 +427,7 @@ test_end
test dtlb_autoload
set_vector kernel, 0
pt_setup 0, 3, 1, 0x1000, 0x1000, 3
pt_setup 0, 3, 1, BASE + 0x1000, 0x1000, 3
assert_no_auto_tlb
l8ui a1, a3, 0
@ -418,8 +442,8 @@ test autoload_load_store_privilege
set_vector kernel, 0
set_vector double, 2f
pt_setup 0, 3, 0, 0x2000, 0x2000, 3
movi a3, 0x2004
pt_setup 0, 3, 0, BASE + 0x2000, 0x2000, 3
movi a3, BASE + 0x2004
assert_no_auto_tlb
movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
@ -441,7 +465,7 @@ test_end
test autoload_pte_load_prohibited
set_vector kernel, 2f
pt_setup 0, 3, 0, 0x3000, 0, 0xc
pt_setup 0, 3, 0, BASE + 0x3000, 0, 0xc
assert_no_auto_tlb
1:
l32i a2, a3, 0
@ -458,7 +482,7 @@ test_end
test autoload_pt_load_prohibited
set_vector kernel, 2f
pt_setup 0, 0xc, 0, 0x4000, 0x4000, 3
pt_setup 0, 0xc, 0, BASE + 0x4000, 0x4000, 3
assert_no_auto_tlb
1:
l32i a2, a3, 0
@ -474,8 +498,8 @@ test_end
test autoload_pt_privilege
set_vector kernel, 2f
pt_setup 0, 3, 1, 0x5000, 0, 3
go_ring 1, 0, 0x5001
pt_setup 0, 3, 1, BASE + 0x5000, 0, 3
go_ring 1, 0, BASE + 0x5001
l8ui a2, a3, 0
1:
@ -491,8 +515,8 @@ test_end
test autoload_pte_privilege
set_vector kernel, 2f
pt_setup 0, 3, 0, 0x6000, 0, 3
go_ring 1, 0, 0x6001
pt_setup 0, 3, 0, BASE + 0x6000, 0, 3
go_ring 1, 0, BASE + 0x6001
1:
l8ui a2, a3, 0
syscall
@ -507,9 +531,9 @@ test_end
test autoload_3_level_pt
set_vector kernel, 2f
pt_setup 1, 3, 1, 0x00400000, 0, 3
pt_setup 1, 3, 1, 0x80001000, 0x2000000, 3
go_ring 1, 0, 0x00400001
pt_setup 1, 3, 1, BASE + 0x00400000, 0, 3
pt_setup 1, 3, 1, TLB_BASE + ((BASE + 0x00400000) >> 10), 0x2000000, 3
go_ring 1, 0, BASE + 0x00400001
1:
l8ui a2, a3, 0
syscall
@ -526,14 +550,14 @@ test cross_page_insn
set_vector kernel, 2f
movi a2, 0x04000003 /* PPN */
movi a3, 0x00007000 /* VPN */
movi a3, BASE + 0x00007000 /* VPN */
witlb a2, a3
wdtlb a2, a3
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
wdtlb a2, a3
movi a2, 0x00007fff
movi a2, BASE + 0x00007fff
movi a3, 20f
movi a4, 21f
sub a4, a4, a3
@ -543,8 +567,8 @@ test cross_page_insn
addi a2, a2, 1
addi a3, a3, 1
1:
movi a2, 0x00007fff
movi a3, 0x00008000
movi a2, BASE + 0x00007fff
movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: OK */
jx a2
@ -560,20 +584,20 @@ test cross_page_insn
movi a3, 1
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x8002
movi a3, BASE + 0x8002
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007fff
movi a3, BASE + 0x00007fff
assert ne, a2, a3
reset_ps
set_vector kernel, 3f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
movi a2, 0x00007fff
movi a3, 0x00008000
movi a2, BASE + 0x00007fff
movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: OK */
jx a2
3:
@ -581,22 +605,22 @@ test cross_page_insn
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7fff
movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007fff
movi a3, BASE + 0x00007fff
assert eq, a2, a3
reset_ps
set_vector kernel, 4f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
movi a2, 0x04000003 /* PPN */
wdtlb a2, a3
movi a2, 0x00007fff
movi a3, 0x00008000
movi a2, BASE + 0x00007fff
movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: FAIL */
jx a2
4:
@ -604,20 +628,20 @@ test cross_page_insn
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7fff
movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007fff
movi a3, BASE + 0x00007fff
assert eq, a2, a3
reset_ps
set_vector kernel, 5f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
movi a2, 0x00007fff
movi a3, 0x00008000
movi a2, BASE + 0x00007fff
movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: FAIL */
jx a2
5:
@ -625,10 +649,10 @@ test cross_page_insn
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7fff
movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007fff
movi a3, BASE + 0x00007fff
assert eq, a2, a3
test_end
@ -636,14 +660,14 @@ test cross_page_tb
set_vector kernel, 2f
movi a2, 0x04000003 /* PPN */
movi a3, 0x00007000 /* VPN */
movi a3, BASE + 0x00007000 /* VPN */
witlb a2, a3
wdtlb a2, a3
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
wdtlb a2, a3
movi a2, 0x00007ffc
movi a2, BASE + 0x00007ffc
movi a3, 20f
movi a4, 21f
sub a4, a4, a3
@ -653,8 +677,8 @@ test cross_page_tb
addi a2, a2, 1
addi a3, a3, 1
1:
movi a2, 0x00007ffc
movi a3, 0x00008000
movi a2, BASE + 0x00007ffc
movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: OK */
jx a2
@ -670,20 +694,20 @@ test cross_page_tb
movi a3, 1
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7fff
movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007ffc
movi a3, BASE + 0x00007ffc
assert ne, a2, a3
reset_ps
set_vector kernel, 3f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
movi a2, 0x00007ffc
movi a3, 0x00008000
movi a2, BASE + 0x00007ffc
movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: OK */
jx a2
3:
@ -691,22 +715,22 @@ test cross_page_tb
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7ffc
movi a3, BASE + 0x7ffc
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007ffc
movi a3, BASE + 0x00007ffc
assert eq, a2, a3
reset_ps
set_vector kernel, 4f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
witlb a2, a3
movi a2, 0x04000003 /* PPN */
wdtlb a2, a3
movi a2, 0x00007ffc
movi a3, 0x00008000
movi a2, BASE + 0x00007ffc
movi a3, BASE + 0x00008000
/* DTLB: OK, ITLB: FAIL */
jx a2
4:
@ -714,20 +738,20 @@ test cross_page_tb
movi a3, 20
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7fff
movi a3, BASE + 0x7fff
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007ffc
movi a3, BASE + 0x00007ffc
assert ne, a2, a3
reset_ps
set_vector kernel, 5f
movi a2, 0x0400000c /* PPN */
movi a3, 0x00008000 /* VPN */
movi a3, BASE + 0x00008000 /* VPN */
wdtlb a2, a3
movi a2, 0x00007ffc
movi a3, 0x00008000
movi a2, BASE + 0x00007ffc
movi a3, BASE + 0x00008000
/* DTLB: FAIL, ITLB: FAIL */
jx a2
5:
@ -735,10 +759,10 @@ test cross_page_tb
movi a3, 28
assert eq, a2, a3
rsr a2, epc1
movi a3, 0x7ffc
movi a3, BASE + 0x7ffc
assert eq, a2, a3
rsr a2, excsave1
movi a3, 0x00007ffc
movi a3, BASE + 0x00007ffc
assert eq, a2, a3
test_end

10
tests/tcg/xtensa/test_phys_mem.S
View File

@ -2,7 +2,7 @@
test_suite phys_mem
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_HAVE_PTP_MMU
.purgem test_init
@ -13,6 +13,14 @@ test_suite phys_mem
witlb a2, a3
movi a2, 0xc0000000
wsr a2, ptevaddr
#if XCHAL_HAVE_SPANNING_WAY
movi a2, 0xc0000000 | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
movi a2, 0x20000000 | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
#endif
.endm
test inst_fetch_get_pte_no_phys

2
tests/tcg/xtensa/test_sr.S
View File

@ -221,6 +221,8 @@ test_sr_mask /*scompare1*/12, 0, 0
#if XCHAL_HAVE_VECBASE
test_sr vecbase, 1
movi a2, XCHAL_VECBASE_RESET_VADDR
wsr a2, vecbase
#else
test_sr_mask /*vecbase*/231, 0, 0
#endif

68
tests/tcg/xtensa/test_timer.S
View File

@ -38,6 +38,28 @@ test_end
#if XCHAL_NUM_TIMERS
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
#define TIMER0_VECTOR kernel
#else
#define TIMER0_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT))
#endif
#if XCHAL_NUM_TIMERS > 1
#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
#define TIMER1_VECTOR kernel
#else
#define TIMER1_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT))
#endif
#endif
#if XCHAL_NUM_TIMERS > 2
#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
#define TIMER2_VECTOR kernel
#else
#define TIMER2_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT))
#endif
#endif
test ccount_update_deadline
movi a2, 0
wsr a2, intenable
@ -90,9 +112,8 @@ test ccompare
assert nei, a5, 0
test_end
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
test ccompare0_interrupt
set_vector kernel, 2f
set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -115,20 +136,21 @@ test ccompare0_interrupt
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
nop
1:
addi a3, a3, -1
bnez a3, 1b
test_fail
2:
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
test_end
#endif
test_end
#if XCHAL_NUM_TIMERS > 1
test ccompare1_interrupt
set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
set_vector TIMER1_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -148,18 +170,22 @@ test ccompare1_interrupt
movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
loop a3, 1f
nop
1:
addi a3, a3, -1
bnez a3, 1b
test_fail
2:
#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
test_end
#endif
#if XCHAL_NUM_TIMERS > 2
test ccompare2_interrupt
set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
set_vector TIMER2_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -177,17 +203,21 @@ test ccompare2_interrupt
movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
loop a3, 1f
nop
1:
addi a3, a3, -1
bnez a3, 1b
test_fail
2:
#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
test_end
#endif
test ccompare_interrupt_masked
set_vector kernel, 2f
set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -197,7 +227,7 @@ test ccompare_interrupt_masked
wsr a2, ccompare2
#endif
movi a3, 2 * WAIT_LOOPS
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
@ -211,17 +241,20 @@ test ccompare_interrupt_masked
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
nop
1:
addi a3, a3, -1
bnez a3, 1b
test_fail
2:
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
test_end
test ccompare_interrupt_masked_waiti
set_vector kernel, 2f
set_vector TIMER0_VECTOR, 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@ -231,7 +264,6 @@ test ccompare_interrupt_masked_waiti
wsr a2, ccompare2
#endif
movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
@ -247,8 +279,10 @@ test ccompare_interrupt_masked_waiti
waiti 0
test_fail
2:
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
test_end
#endif