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target/riscv: Fix checkpatch warning may triggered in csr_ops table
Fix the lines with over 80 characters Fix the lines which are obviously misalgined with other lines in the same group Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
Alistair Francis
parent
756b0374dc
commit
108c4f26ce
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@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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#if !defined(CONFIG_USER_ONLY)
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/* Machine Timers and Counters */
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[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter},
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[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh},
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[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh},
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[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
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write_mhpmcounter },
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[CSR_MINSTRET] = { "minstret", any, read_hpmcounter,
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write_mhpmcounter },
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[CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh,
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write_mhpmcounterh },
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[CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh,
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write_mhpmcounterh },
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/* Machine Information Registers */
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[CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
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@ -3507,21 +3511,23 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* Machine Trap Setup */
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL,
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read_mstatus_i128 },
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[CSR_MISA] = { "misa", any, read_misa, write_misa, NULL,
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read_misa_i128 },
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[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus,
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NULL, read_mstatus_i128 },
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[CSR_MISA] = { "misa", any, read_misa, write_misa,
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NULL, read_misa_i128 },
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[CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg },
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[CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
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[CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
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[CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
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[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren },
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[CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
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write_mcounteren },
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[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
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[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
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write_mstatush },
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/* Machine Trap Handling */
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL,
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read_mscratch_i128, write_mscratch_i128 },
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[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch,
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NULL, read_mscratch_i128, write_mscratch_i128 },
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[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
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[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
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[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
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@ -3559,15 +3565,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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/* Supervisor Trap Setup */
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL,
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read_sstatus_i128 },
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[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
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NULL, read_sstatus_i128 },
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[CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
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[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
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[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
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[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
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write_scounteren },
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/* Supervisor Trap Handling */
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
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read_sscratch_i128, write_sscratch_i128 },
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[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
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NULL, read_sscratch_i128, write_sscratch_i128 },
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[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
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[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
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[CSR_STVAL] = { "stval", smode, read_stval, write_stval },
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@ -3600,7 +3607,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren,
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[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
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write_hcounteren,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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@ -3612,12 +3620,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta,
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[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
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write_htimedelta,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah,
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[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
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write_htimedeltah,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus,
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[CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
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write_vsstatus,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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@ -3625,7 +3636,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch,
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[CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
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write_vsscratch,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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[CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
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.min_priv_ver = PRIV_VERSION_1_12_0 },
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@ -3643,14 +3655,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
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[CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
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[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
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[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
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[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
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[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl,
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write_hvictl },
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[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1,
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write_hviprio1 },
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[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2,
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write_hviprio2 },
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/*
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* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
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*/
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[CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect },
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[CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL,
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rmw_xiselect },
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[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
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/* VS-Level Interrupts (H-extension with AIA) */
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@ -3658,11 +3674,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
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/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
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[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
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[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
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[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL,
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rmw_hidelegh },
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[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
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write_ignore },
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[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
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[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
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[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
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[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
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write_hviprio1h },
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[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
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write_hviprio2h },
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[CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
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[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
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@ -3698,16 +3718,22 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* User Pointer Masking */
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[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
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[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
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[CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
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[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
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write_upmmask },
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[CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
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write_upmbase },
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/* Machine Pointer Masking */
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[CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
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[CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
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[CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
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[CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
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write_mpmmask },
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[CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
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write_mpmbase },
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/* Supervisor Pointer Masking */
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[CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
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[CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
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[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
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[CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
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write_spmmask },
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[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
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write_spmbase },
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/* Performance Counters */
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[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
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@ -3800,7 +3826,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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write_mhpmcounter },
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[CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
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write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 },
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write_mcountinhibit,
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.min_priv_ver = PRIV_VERSION_1_11_0 },
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[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
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write_mhpmevent },
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