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target/mips: simplify gen_compute_imm_branch logic 

One of the Travis builds was complaining about:

  qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
       return (TCGCond)(c ^ 1);
  ../target/mips/translate.c:20031:13: note: ‘cond’ was declared here
       TCGCond cond;

Rather than figure out exactly which one was causing the complaint I
just defaulted to TCG_COND_ALWAYS and allowed that state to double up
for the now defunct bcond_compute variable.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200909112742.25730-5-alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée 2020-09-09 12:27:35 +01:00
parent 7f80868744
commit 102661430c
1 changed files with 2 additions and 10 deletions
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12
target/mips/translate.c
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@ -20028,8 +20028,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
int rt, int32_t imm, int32_t offset) int rt, int32_t imm, int32_t offset)
{ {
TCGCond cond; TCGCond cond = TCG_COND_ALWAYS;
int bcond_compute = 0;
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new(); TCGv t1 = tcg_temp_new();
@ -20046,7 +20045,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
/* Treat as NOP */ /* Treat as NOP */
goto out; goto out;
} else { } else {
bcond_compute = 1;
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
} }
break; break;
@ -20065,7 +20063,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
tcg_gen_shri_tl(t0, t0, imm); tcg_gen_shri_tl(t0, t0, imm);
tcg_gen_andi_tl(t0, t0, 1); tcg_gen_andi_tl(t0, t0, 1);
tcg_gen_movi_tl(t1, 0); tcg_gen_movi_tl(t1, 0);
bcond_compute = 1;
if (opc == NM_BBEQZC) { if (opc == NM_BBEQZC) {
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
} else { } else {
@ -20080,7 +20077,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
} else if (rt == 0 && imm != 0) { } else if (rt == 0 && imm != 0) {
/* Unconditional branch */ /* Unconditional branch */
} else { } else {
bcond_compute = 1;
cond = TCG_COND_NE; cond = TCG_COND_NE;
} }
break; break;
@ -20088,24 +20084,20 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
if (rt == 0 && imm == 0) { if (rt == 0 && imm == 0) {
/* Unconditional branch */ /* Unconditional branch */
} else { } else {
bcond_compute = 1;
cond = TCG_COND_GE; cond = TCG_COND_GE;
} }
break; break;
case NM_BLTIC: case NM_BLTIC:
bcond_compute = 1;
cond = TCG_COND_LT; cond = TCG_COND_LT;
break; break;
case NM_BGEIUC: case NM_BGEIUC:
if (rt == 0 && imm == 0) { if (rt == 0 && imm == 0) {
/* Unconditional branch */ /* Unconditional branch */
} else { } else {
bcond_compute = 1;
cond = TCG_COND_GEU; cond = TCG_COND_GEU;
} }
break; break;
case NM_BLTIUC: case NM_BLTIUC:
bcond_compute = 1;
cond = TCG_COND_LTU; cond = TCG_COND_LTU;
break; break;
default: default:
@ -20118,7 +20110,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
clear_branch_hflags(ctx); clear_branch_hflags(ctx);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
if (bcond_compute == 0) { if (cond == TCG_COND_ALWAYS) {
/* Uncoditional compact branch */ /* Uncoditional compact branch */
gen_goto_tb(ctx, 0, ctx->btarget); gen_goto_tb(ctx, 0, ctx->btarget);
} else { } else {