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tcg/riscv: Implement vector sat/mul ops 

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-9-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
TANG Tiancheng 2024-10-07 10:56:56 +08:00 committed by Richard Henderson
parent dc9cd4ec12
commit 101c1ef562
2 changed files with 43 additions and 2 deletions
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41
tcg/riscv/tcg-target.c.inc
View File

@ -284,6 +284,16 @@ typedef enum {
OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
OPC_VXOR_VI = 0x2c000057 | V_OPIVI,
OPC_VMUL_VV = 0x94000057 | V_OPMVV,
OPC_VSADD_VV = 0x84000057 | V_OPIVV,
OPC_VSADD_VI = 0x84000057 | V_OPIVI,
OPC_VSSUB_VV = 0x8c000057 | V_OPIVV,
OPC_VSSUB_VI = 0x8c000057 | V_OPIVI,
OPC_VSADDU_VV = 0x80000057 | V_OPIVV,
OPC_VSADDU_VI = 0x80000057 | V_OPIVI,
OPC_VSSUBU_VV = 0x88000057 | V_OPIVV,
OPC_VSSUBU_VI = 0x88000057 | V_OPIVI,
OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
@ -2376,6 +2386,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0);
break;
case INDEX_op_mul_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2);
break;
case INDEX_op_ssadd_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv_vi(s, OPC_VSADD_VV, OPC_VSADD_VI, a0, a1, a2, c2);
break;
case INDEX_op_sssub_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv_vi(s, OPC_VSSUB_VV, OPC_VSSUB_VI, a0, a1, a2, c2);
break;
case INDEX_op_usadd_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv_vi(s, OPC_VSADDU_VV, OPC_VSADDU_VI, a0, a1, a2, c2);
break;
case INDEX_op_ussub_vec:
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2);
break;
case INDEX_op_cmp_vec:
tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2,
-1, true, 0, true);
@ -2407,6 +2437,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
case INDEX_op_mul_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
return 1;
@ -2567,9 +2602,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
return C_O1_I2(v, v, vK);
case INDEX_op_sub_vec:
return C_O1_I2(v, vK, v);
case INDEX_op_mul_vec:
return C_O1_I2(v, v, v);
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL);
case INDEX_op_cmpsel_vec:

4
tcg/riscv/tcg-target.h
View File

@ -160,8 +160,8 @@ typedef enum {
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 1