mirror of https://github.com/xemu-project/xemu.git
sun4u: move initialisation of all ISABus devices into ebus_realize()
This belongs in the PCI-ISA bridge rather than at the machine level. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
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c796eddaad
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@ -85,6 +85,7 @@ typedef struct EbusState {
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PCIDevice parent_obj;
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PCIDevice parent_obj;
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ISABus *isa_bus;
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ISABus *isa_bus;
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uint64_t console_serial_base;
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MemoryRegion bar0;
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MemoryRegion bar0;
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MemoryRegion bar1;
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MemoryRegion bar1;
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} EbusState;
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} EbusState;
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@ -234,7 +235,10 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
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{
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{
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EbusState *s = EBUS(pci_dev);
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EbusState *s = EBUS(pci_dev);
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APBState *apb;
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APBState *apb;
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DeviceState *dev;
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qemu_irq *isa_irq;
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qemu_irq *isa_irq;
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DriveInfo *fd[MAX_FD];
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int i;
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s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
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s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
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pci_address_space_io(pci_dev), errp);
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pci_address_space_io(pci_dev), errp);
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@ -252,6 +256,38 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
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isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16);
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isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16);
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isa_bus_irqs(s->isa_bus, isa_irq);
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isa_bus_irqs(s->isa_bus, isa_irq);
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/* Serial ports */
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i = 0;
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if (s->console_serial_base) {
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serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
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0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
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i++;
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}
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serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
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/* Parallel ports */
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parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
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/* Keyboard */
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isa_create_simple(s->isa_bus, "i8042");
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/* Floppy */
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for (i = 0; i < MAX_FD; i++) {
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fd[i] = drive_get(IF_FLOPPY, 0, i);
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}
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dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
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if (fd[0]) {
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qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
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&error_abort);
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}
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if (fd[1]) {
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qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
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&error_abort);
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}
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qdev_prop_set_uint32(dev, "dma", -1);
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qdev_init_nofail(dev);
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/* PCI */
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pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
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pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
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pci_dev->config[0x05] = 0x00;
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pci_dev->config[0x05] = 0x00;
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pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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@ -267,15 +303,23 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
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pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
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pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
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}
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}
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static Property ebus_properties[] = {
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DEFINE_PROP_UINT64("console-serial-base", EbusState,
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console_serial_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ebus_class_init(ObjectClass *klass, void *data)
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static void ebus_class_init(ObjectClass *klass, void *data)
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{
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = ebus_realize;
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k->realize = ebus_realize;
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k->vendor_id = PCI_VENDOR_ID_SUN;
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k->vendor_id = PCI_VENDOR_ID_SUN;
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k->device_id = PCI_DEVICE_ID_SUN_EBUS;
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k->device_id = PCI_DEVICE_ID_SUN_EBUS;
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k->revision = 0x01;
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k->revision = 0x01;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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dc->props = ebus_properties;
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}
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}
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static const TypeInfo ebus_info = {
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static const TypeInfo ebus_info = {
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@ -440,11 +484,9 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
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uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
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PCIBus *pci_bus, *pci_busA, *pci_busB;
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PCIBus *pci_bus, *pci_busA, *pci_busB;
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PCIDevice *ebus, *pci_dev;
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PCIDevice *ebus, *pci_dev;
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ISABus *isa_bus;
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SysBusDevice *s;
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SysBusDevice *s;
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qemu_irq *ivec_irqs;
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qemu_irq *ivec_irqs;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DriveInfo *fd[MAX_FD];
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DeviceState *dev;
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DeviceState *dev;
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FWCfgState *fw_cfg;
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FWCfgState *fw_cfg;
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NICInfo *nd;
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NICInfo *nd;
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@ -471,20 +513,10 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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pci_busB->slot_reserved_mask = 0xfffffff0;
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pci_busB->slot_reserved_mask = 0xfffffff0;
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ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
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ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
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qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
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hwdef->console_serial_base);
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qdev_init_nofail(DEVICE(ebus));
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qdev_init_nofail(DEVICE(ebus));
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isa_bus = EBUS(ebus)->isa_bus;
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i = 0;
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if (hwdef->console_serial_base) {
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serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
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NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
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i++;
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}
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serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS);
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parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
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pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
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pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
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memset(&macaddr, 0, sizeof(MACAddr));
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memset(&macaddr, 0, sizeof(MACAddr));
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@ -523,24 +555,6 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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qdev_init_nofail(&pci_dev->qdev);
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qdev_init_nofail(&pci_dev->qdev);
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pci_ide_create_devs(pci_dev, hd);
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pci_ide_create_devs(pci_dev, hd);
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isa_create_simple(isa_bus, "i8042");
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/* Floppy */
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for(i = 0; i < MAX_FD; i++) {
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fd[i] = drive_get(IF_FLOPPY, 0, i);
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}
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dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
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if (fd[0]) {
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qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
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&error_abort);
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}
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if (fd[1]) {
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qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
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&error_abort);
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}
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qdev_prop_set_uint32(dev, "dma", -1);
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qdev_init_nofail(dev);
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/* Map NVRAM into I/O (ebus) space */
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/* Map NVRAM into I/O (ebus) space */
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nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
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nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
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s = SYS_BUS_DEVICE(nvram);
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s = SYS_BUS_DEVICE(nvram);
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