mirror of https://github.com/xemu-project/xemu.git
target/microblaze: Fix width of PC and BTARGET
The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
aa28e6d4c7
commit
0f96e96bd5
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@ -231,12 +231,12 @@ typedef struct CPUMBState CPUMBState;
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struct CPUMBState {
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uint32_t debug;
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uint32_t btaken;
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uint64_t btarget;
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uint32_t btarget;
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uint32_t bimm;
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uint32_t imm;
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uint32_t regs[32];
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uint64_t pc;
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uint32_t pc;
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uint64_t msr;
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uint64_t ear;
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uint64_t esr;
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@ -143,7 +143,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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env->msr |= MSR_EIP;
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qemu_log_mask(CPU_LOG_INT,
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"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
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"hw exception at pc=%x ear=%" PRIx64 " "
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"esr=%" PRIx64 " iflags=%x\n",
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env->pc, env->ear,
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env->esr, env->iflags);
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@ -167,8 +167,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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/* was the branch immprefixed?. */
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if (env->bimm) {
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qemu_log_mask(CPU_LOG_INT,
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"bimm exception at pc=%" PRIx64 " "
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"iflags=%x\n",
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"bimm exception at pc=%x iflags=%x\n",
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env->pc, env->iflags);
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env->regs[17] -= 4;
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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@ -186,8 +185,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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env->msr |= MSR_EIP;
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
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"iflags=%x\n",
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"exception at pc=%x ear=%" PRIx64 " iflags=%x\n",
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env->pc, env->ear, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->iflags &= ~(IMM_FLAG | D_FLAG);
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@ -224,8 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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}
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#endif
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qemu_log_mask(CPU_LOG_INT,
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"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
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"iflags=%x\n",
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"interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
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env->pc, env->msr, t, env->iflags);
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env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
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@ -242,9 +239,8 @@ void mb_cpu_do_interrupt(CPUState *cs)
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assert(!(env->iflags & D_FLAG));
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t = (env->msr & (MSR_VM | MSR_UM)) << 1;
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qemu_log_mask(CPU_LOG_INT,
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"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
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"iflags=%x\n",
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env->pc, env->msr, t, env->iflags);
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"break at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
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env->pc, env->msr, t, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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env->msr |= t;
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@ -250,8 +250,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
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if (rn == MMU_R_TLBHI) {
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if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
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qemu_log_mask(LOG_GUEST_ERROR,
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"invalidating index %x at pc=%" PRIx64 "\n",
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i, env->pc);
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"invalidating index %x at pc=%x\n",
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i, env->pc);
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env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
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mmu_flush_idx(env, i);
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}
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@ -75,12 +75,12 @@ void helper_debug(CPUMBState *env)
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{
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int i;
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qemu_log("PC=%" PRIx64 "\n", env->pc);
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qemu_log("PC=%08x\n", env->pc);
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qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
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"debug[%x] imm=%x iflags=%x\n",
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env->msr, env->esr, env->ear,
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env->debug, env->imm, env->iflags);
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qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
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qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
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env->btaken, env->btarget,
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(env->msr & MSR_UM) ? "user" : "kernel",
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(env->msr & MSR_UMS) ? "user" : "kernel",
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@ -55,7 +55,7 @@
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static TCGv_i32 env_debug;
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static TCGv_i32 cpu_R[32];
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static TCGv_i64 cpu_pc;
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static TCGv_i32 cpu_pc;
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static TCGv_i64 cpu_msr;
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static TCGv_i64 cpu_ear;
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static TCGv_i64 cpu_esr;
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@ -64,7 +64,7 @@ static TCGv_i64 cpu_btr;
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static TCGv_i64 cpu_edr;
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static TCGv_i32 env_imm;
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static TCGv_i32 env_btaken;
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static TCGv_i64 env_btarget;
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static TCGv_i32 cpu_btarget;
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static TCGv_i32 env_iflags;
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static TCGv env_res_addr;
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static TCGv_i32 env_res_val;
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@ -123,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
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TCGv_i32 tmp = tcg_const_i32(index);
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t_sync_flags(dc);
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tcg_gen_movi_i64(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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dc->is_jmp = DISAS_UPDATE;
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@ -142,10 +142,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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{
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if (use_goto_tb(dc, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_i64(cpu_pc, dest);
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb(dc->tb, n);
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} else {
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tcg_gen_movi_i64(cpu_pc, dest);
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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@ -509,7 +509,7 @@ static void dec_msr(DisasContext *dc)
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msr_write(dc, t0);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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tcg_gen_movi_i64(cpu_pc, dc->pc + 4);
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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dc->is_jmp = DISAS_UPDATE;
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return;
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}
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@ -850,7 +850,7 @@ static inline void sync_jmpstate(DisasContext *dc)
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tcg_gen_movi_i32(env_btaken, 1);
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}
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dc->jmp = JMP_INDIRECT;
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tcg_gen_movi_i64(env_btarget, dc->jmp_pc);
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tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc);
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}
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}
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@ -1019,7 +1019,7 @@ static void dec_load(DisasContext *dc)
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i64(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
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tcg_temp_free_i32(t0);
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@ -1139,7 +1139,7 @@ static void dec_store(DisasContext *dc)
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TCGv_i32 treg = tcg_const_i32(dc->rd);
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TCGv_i32 tsize = tcg_const_i32(size - 1);
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tcg_gen_movi_i64(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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/* FIXME: if the alignment is wrong, we should restore the value
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* in memory. One possible way to achieve this is to probe
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* the MMU prior to the memaccess, thay way we could put
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@ -1187,18 +1187,15 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc,
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}
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}
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static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
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static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false)
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{
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TCGv_i64 tmp_btaken = tcg_temp_new_i64();
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TCGv_i64 tmp_zero = tcg_const_i64(0);
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TCGv_i32 zero = tcg_const_i32(0);
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tcg_gen_extu_i32_i64(tmp_btaken, env_btaken);
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tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc,
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tmp_btaken, tmp_zero,
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tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc,
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env_btaken, zero,
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pc_true, pc_false);
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tcg_temp_free_i64(tmp_btaken);
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tcg_temp_free_i64(tmp_zero);
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tcg_temp_free_i32(zero);
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}
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static void dec_setup_dslot(DisasContext *dc)
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@ -1229,14 +1226,12 @@ static void dec_bcc(DisasContext *dc)
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if (dec_alu_op_b_is_small_imm(dc)) {
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int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
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tcg_gen_movi_i64(env_btarget, dc->pc + offset);
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tcg_gen_movi_i32(cpu_btarget, dc->pc + offset);
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dc->jmp = JMP_DIRECT_CC;
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dc->jmp_pc = dc->pc + offset;
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} else {
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dc->jmp = JMP_INDIRECT;
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tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc)));
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tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc);
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tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
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}
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eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]);
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}
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@ -1277,7 +1272,7 @@ static void dec_br(DisasContext *dc)
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tcg_gen_st_i32(tmp_1, cpu_env,
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-offsetof(MicroBlazeCPU, env)
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+offsetof(CPUState, halted));
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tcg_gen_movi_i64(cpu_pc, dc->pc + 4);
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tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
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gen_helper_raise_exception(cpu_env, tmp_hlt);
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tcg_temp_free_i32(tmp_hlt);
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tcg_temp_free_i32(tmp_1);
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@ -1303,7 +1298,7 @@ static void dec_br(DisasContext *dc)
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dc->jmp = JMP_INDIRECT;
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if (abs) {
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tcg_gen_movi_i32(env_btaken, 1);
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tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc)));
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tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc)));
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if (link && !dslot) {
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if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
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t_gen_raise_exception(dc, EXCP_BREAK);
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@ -1321,9 +1316,7 @@ static void dec_br(DisasContext *dc)
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dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
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} else {
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tcg_gen_movi_i32(env_btaken, 1);
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tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc)));
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tcg_gen_addi_i64(env_btarget, env_btarget, dc->pc);
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tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
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}
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}
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}
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@ -1387,7 +1380,6 @@ static inline void do_rte(DisasContext *dc)
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static void dec_rts(DisasContext *dc)
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{
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unsigned int b_bit, i_bit, e_bit;
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TCGv_i64 tmp64;
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i_bit = dc->ir & (1 << 21);
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b_bit = dc->ir & (1 << 22);
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@ -1413,13 +1405,7 @@ static void dec_rts(DisasContext *dc)
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dc->jmp = JMP_INDIRECT;
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tcg_gen_movi_i32(env_btaken, 1);
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tmp64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(env_btarget, *(dec_alu_op_b(dc)));
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tcg_gen_extu_i32_i64(tmp64, cpu_R[dc->ra]);
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tcg_gen_add_i64(env_btarget, env_btarget, tmp64);
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tcg_gen_andi_i64(env_btarget, env_btarget, UINT32_MAX);
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tcg_temp_free_i64(tmp64);
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tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc));
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}
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static int dec_check_fpuv2(DisasContext *dc)
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@ -1676,7 +1662,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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#if SIM_COMPAT
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
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tcg_gen_movi_i64(cpu_pc, dc->pc);
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tcg_gen_movi_i32(cpu_pc, dc->pc);
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gen_helper_debug();
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}
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#endif
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@ -1718,10 +1704,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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dc->tb_flags &= ~D_FLAG;
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/* If it is a direct jump, try direct chaining. */
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if (dc->jmp == JMP_INDIRECT) {
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TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
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eval_cond_jmp(dc, env_btarget, tmp_pc);
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tcg_temp_free_i64(tmp_pc);
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TCGv_i32 tmp_pc = tcg_const_i32(dc->pc);
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eval_cond_jmp(dc, cpu_btarget, tmp_pc);
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tcg_temp_free_i32(tmp_pc);
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dc->is_jmp = DISAS_JUMP;
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} else if (dc->jmp == JMP_DIRECT) {
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t_sync_flags(dc);
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@ -1754,7 +1739,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
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if (dc->tb_flags & D_FLAG) {
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dc->is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i64(cpu_pc, npc);
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tcg_gen_movi_i32(cpu_pc, npc);
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sync_jmpstate(dc);
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} else
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npc = dc->jmp_pc;
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@ -1764,7 +1749,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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if (dc->is_jmp == DISAS_NEXT
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&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
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dc->is_jmp = DISAS_UPDATE;
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tcg_gen_movi_i64(cpu_pc, npc);
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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t_sync_flags(dc);
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@ -1772,7 +1757,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
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if (dc->is_jmp != DISAS_JUMP) {
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tcg_gen_movi_i64(cpu_pc, npc);
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tcg_gen_movi_i32(cpu_pc, npc);
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}
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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@ -1822,7 +1807,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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return;
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}
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qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n",
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qemu_fprintf(f, "IN: PC=%x %s\n",
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env->pc, lookup_symbol(env->pc));
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qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
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"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
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@ -1830,8 +1815,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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env->msr, env->esr, env->ear,
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env->debug, env->imm, env->iflags, env->fsr,
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env->btr);
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qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
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"eip=%d ie=%d\n",
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qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
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env->btaken, env->btarget,
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(env->msr & MSR_UM) ? "user" : "kernel",
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(env->msr & MSR_UMS) ? "user" : "kernel",
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@ -1869,7 +1853,7 @@ void mb_tcg_init(void)
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env_imm = tcg_global_mem_new_i32(cpu_env,
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offsetof(CPUMBState, imm),
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"imm");
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env_btarget = tcg_global_mem_new_i64(cpu_env,
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cpu_btarget = tcg_global_mem_new_i32(cpu_env,
|
||||
offsetof(CPUMBState, btarget),
|
||||
"btarget");
|
||||
env_btaken = tcg_global_mem_new_i32(cpu_env,
|
||||
|
@ -1888,7 +1872,7 @@ void mb_tcg_init(void)
|
|||
}
|
||||
|
||||
cpu_pc =
|
||||
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
|
||||
tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc");
|
||||
cpu_msr =
|
||||
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
|
||||
cpu_ear =
|
||||
|
|
Loading…
Reference in New Issue