mirror of https://github.com/xemu-project/xemu.git
target/arm: Implement the SET* instructions
Implement the SET* instructions which collectively implement a "memset" operation. These come in a set of three, eg SETP (prologue), SETM (main), SETE (epilogue), and each of those has different flavours to indicate whether memory accesses should be unpriv or non-temporal. This commit does not include the "memset with tag setting" SETG* instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230912140434.1333369-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
8163998920
commit
0e92818887
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@ -554,3 +554,19 @@ LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
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STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
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STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
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STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
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# Memory operations (memset, memcpy, memmove)
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# Each of these comes in a set of three, eg SETP (prologue), SETM (main),
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# SETE (epilogue), and each of those has different flavours to
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# indicate whether memory accesses should be unpriv or non-temporal.
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# We don't distinguish temporal and non-temporal accesses, but we
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# do need to report it in syndrome register values.
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# Memset
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&set rs rn rd unpriv nontemp
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# op2 bit 1 is nontemporal bit
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@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set
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SETP 00 011001110 ..... 00 . . 01 ..... ..... @set
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SETM 00 011001110 ..... 01 . . 01 ..... ..... @set
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SETE 00 011001110 ..... 10 . . 01 ..... ..... @set
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@ -968,3 +968,347 @@ void HELPER(unaligned_access)(CPUARMState *env, uint64_t addr,
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arm_cpu_do_unaligned_access(env_cpu(env), addr, access_type,
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mmu_idx, GETPC());
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}
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/* Memory operations (memset, memmove, memcpy) */
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/*
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* Return true if the CPY* and SET* insns can execute; compare
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* pseudocode CheckMOPSEnabled(), though we refactor it a little.
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*/
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static bool mops_enabled(CPUARMState *env)
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{
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int el = arm_current_el(env);
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if (el < 2 &&
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(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
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!(arm_hcrx_el2_eff(env) & HCRX_MSCEN)) {
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return false;
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}
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if (el == 0) {
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if (!el_is_in_host(env, 0)) {
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return env->cp15.sctlr_el[1] & SCTLR_MSCEN;
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} else {
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return env->cp15.sctlr_el[2] & SCTLR_MSCEN;
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}
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}
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return true;
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}
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static void check_mops_enabled(CPUARMState *env, uintptr_t ra)
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{
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if (!mops_enabled(env)) {
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raise_exception_ra(env, EXCP_UDEF, syn_uncategorized(),
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exception_target_el(env), ra);
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}
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}
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/*
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* Return the target exception level for an exception due
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* to mismatched arguments in a FEAT_MOPS copy or set.
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* Compare pseudocode MismatchedCpySetTargetEL()
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*/
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static int mops_mismatch_exception_target_el(CPUARMState *env)
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{
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int el = arm_current_el(env);
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if (el > 1) {
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return el;
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}
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if (el == 0 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
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return 2;
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}
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if (el == 1 && (arm_hcrx_el2_eff(env) & HCRX_MCE2)) {
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return 2;
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}
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return 1;
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}
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/*
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* Check whether an M or E instruction was executed with a CF value
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* indicating the wrong option for this implementation.
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* Assumes we are always Option A.
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*/
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static void check_mops_wrong_option(CPUARMState *env, uint32_t syndrome,
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uintptr_t ra)
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{
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if (env->CF != 0) {
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syndrome |= 1 << 17; /* Set the wrong-option bit */
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raise_exception_ra(env, EXCP_UDEF, syndrome,
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mops_mismatch_exception_target_el(env), ra);
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}
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}
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/*
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* Return the maximum number of bytes we can transfer starting at addr
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* without crossing a page boundary.
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*/
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static uint64_t page_limit(uint64_t addr)
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{
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return TARGET_PAGE_ALIGN(addr + 1) - addr;
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}
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/*
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* Perform part of a memory set on an area of guest memory starting at
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* toaddr (a dirty address) and extending for setsize bytes.
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*
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* Returns the number of bytes actually set, which might be less than
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* setsize; the caller should loop until the whole set has been done.
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* The caller should ensure that the guest registers are correct
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* for the possibility that the first byte of the set encounters
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* an exception or watchpoint. We guarantee not to take any faults
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* for bytes other than the first.
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*/
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static uint64_t set_step(CPUARMState *env, uint64_t toaddr,
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uint64_t setsize, uint32_t data, int memidx,
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uint32_t *mtedesc, uintptr_t ra)
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{
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void *mem;
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setsize = MIN(setsize, page_limit(toaddr));
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if (*mtedesc) {
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uint64_t mtesize = mte_mops_probe(env, toaddr, setsize, *mtedesc);
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if (mtesize == 0) {
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/* Trap, or not. All CPU state is up to date */
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mte_check_fail(env, *mtedesc, toaddr, ra);
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/* Continue, with no further MTE checks required */
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*mtedesc = 0;
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} else {
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/* Advance to the end, or to the tag mismatch */
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setsize = MIN(setsize, mtesize);
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}
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}
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toaddr = useronly_clean_ptr(toaddr);
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/*
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* Trapless lookup: returns NULL for invalid page, I/O,
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* watchpoints, clean pages, etc.
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*/
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mem = tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, memidx);
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#ifndef CONFIG_USER_ONLY
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if (unlikely(!mem)) {
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/*
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* Slow-path: just do one byte write. This will handle the
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* watchpoint, invalid page, etc handling correctly.
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* For clean code pages, the next iteration will see
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* the page dirty and will use the fast path.
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*/
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cpu_stb_mmuidx_ra(env, toaddr, data, memidx, ra);
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return 1;
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}
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#endif
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/* Easy case: just memset the host memory */
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memset(mem, data, setsize);
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return setsize;
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}
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typedef uint64_t StepFn(CPUARMState *env, uint64_t toaddr,
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uint64_t setsize, uint32_t data,
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int memidx, uint32_t *mtedesc, uintptr_t ra);
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/* Extract register numbers from a MOPS exception syndrome value */
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static int mops_destreg(uint32_t syndrome)
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{
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return extract32(syndrome, 10, 5);
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}
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static int mops_srcreg(uint32_t syndrome)
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{
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return extract32(syndrome, 5, 5);
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}
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static int mops_sizereg(uint32_t syndrome)
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{
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return extract32(syndrome, 0, 5);
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}
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/*
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* Return true if TCMA and TBI bits mean we need to do MTE checks.
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* We only need to do this once per MOPS insn, not for every page.
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*/
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static bool mte_checks_needed(uint64_t ptr, uint32_t desc)
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{
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int bit55 = extract64(ptr, 55, 1);
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/*
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* Note that tbi_check() returns true for "access checked" but
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* tcma_check() returns true for "access unchecked".
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*/
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if (!tbi_check(desc, bit55)) {
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return false;
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}
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return !tcma_check(desc, bit55, allocation_tag_from_addr(ptr));
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}
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/*
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* For the Memory Set operation, our implementation chooses
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* always to use "option A", where we update Xd to the final
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* address in the SETP insn, and set Xn to be -(bytes remaining).
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* On SETM and SETE insns we only need update Xn.
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*
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* @env: CPU
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* @syndrome: syndrome value for mismatch exceptions
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* (also contains the register numbers we need to use)
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* @mtedesc: MTE descriptor word
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* @stepfn: function which does a single part of the set operation
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* @is_setg: true if this is the tag-setting SETG variant
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*/
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static void do_setp(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc,
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StepFn *stepfn, bool is_setg, uintptr_t ra)
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{
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/* Prologue: we choose to do up to the next page boundary */
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int rd = mops_destreg(syndrome);
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int rs = mops_srcreg(syndrome);
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int rn = mops_sizereg(syndrome);
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uint8_t data = env->xregs[rs];
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uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
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uint64_t toaddr = env->xregs[rd];
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uint64_t setsize = env->xregs[rn];
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uint64_t stagesetsize, step;
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check_mops_enabled(env, ra);
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if (setsize > INT64_MAX) {
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setsize = INT64_MAX;
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}
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if (!mte_checks_needed(toaddr, mtedesc)) {
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mtedesc = 0;
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}
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stagesetsize = MIN(setsize, page_limit(toaddr));
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while (stagesetsize) {
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env->xregs[rd] = toaddr;
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env->xregs[rn] = setsize;
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step = stepfn(env, toaddr, stagesetsize, data, memidx, &mtedesc, ra);
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toaddr += step;
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setsize -= step;
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stagesetsize -= step;
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}
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/* Insn completed, so update registers to the Option A format */
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env->xregs[rd] = toaddr + setsize;
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env->xregs[rn] = -setsize;
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/* Set NZCV = 0000 to indicate we are an Option A implementation */
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env->NF = 0;
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env->ZF = 1; /* our env->ZF encoding is inverted */
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env->CF = 0;
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env->VF = 0;
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return;
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}
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void HELPER(setp)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc)
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{
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do_setp(env, syndrome, mtedesc, set_step, false, GETPC());
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}
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static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc,
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StepFn *stepfn, bool is_setg, uintptr_t ra)
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{
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/* Main: we choose to do all the full-page chunks */
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CPUState *cs = env_cpu(env);
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int rd = mops_destreg(syndrome);
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int rs = mops_srcreg(syndrome);
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int rn = mops_sizereg(syndrome);
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uint8_t data = env->xregs[rs];
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uint64_t toaddr = env->xregs[rd] + env->xregs[rn];
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uint64_t setsize = -env->xregs[rn];
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uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
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uint64_t step, stagesetsize;
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check_mops_enabled(env, ra);
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/*
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* We're allowed to NOP out "no data to copy" before the consistency
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* checks; we choose to do so.
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*/
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if (env->xregs[rn] == 0) {
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return;
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}
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check_mops_wrong_option(env, syndrome, ra);
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/*
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* Our implementation will work fine even if we have an unaligned
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* destination address, and because we update Xn every time around
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* the loop below and the return value from stepfn() may be less
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* than requested, we might find toaddr is unaligned. So we don't
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* have an IMPDEF check for alignment here.
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*/
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if (!mte_checks_needed(toaddr, mtedesc)) {
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mtedesc = 0;
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}
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/* Do the actual memset: we leave the last partial page to SETE */
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stagesetsize = setsize & TARGET_PAGE_MASK;
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while (stagesetsize > 0) {
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step = stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra);
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toaddr += step;
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setsize -= step;
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stagesetsize -= step;
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env->xregs[rn] = -setsize;
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if (stagesetsize > 0 && unlikely(cpu_loop_exit_requested(cs))) {
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cpu_loop_exit_restore(cs, ra);
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}
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}
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}
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void HELPER(setm)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc)
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{
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do_setm(env, syndrome, mtedesc, set_step, false, GETPC());
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}
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static void do_sete(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc,
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StepFn *stepfn, bool is_setg, uintptr_t ra)
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{
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/* Epilogue: do the last partial page */
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int rd = mops_destreg(syndrome);
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int rs = mops_srcreg(syndrome);
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int rn = mops_sizereg(syndrome);
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uint8_t data = env->xregs[rs];
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uint64_t toaddr = env->xregs[rd] + env->xregs[rn];
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uint64_t setsize = -env->xregs[rn];
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uint32_t memidx = FIELD_EX32(mtedesc, MTEDESC, MIDX);
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uint64_t step;
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check_mops_enabled(env, ra);
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/*
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* We're allowed to NOP out "no data to copy" before the consistency
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* checks; we choose to do so.
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*/
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if (setsize == 0) {
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return;
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}
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check_mops_wrong_option(env, syndrome, ra);
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/*
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* Our implementation has no address alignment requirements, but
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* we do want to enforce the "less than a page" size requirement,
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* so we don't need to have the "check for interrupts" here.
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*/
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if (setsize >= TARGET_PAGE_SIZE) {
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raise_exception_ra(env, EXCP_UDEF, syndrome,
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mops_mismatch_exception_target_el(env), ra);
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}
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if (!mte_checks_needed(toaddr, mtedesc)) {
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mtedesc = 0;
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}
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/* Do the actual memset */
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while (setsize > 0) {
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step = stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra);
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toaddr += step;
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setsize -= step;
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env->xregs[rn] = -setsize;
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}
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}
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void HELPER(sete)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc)
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{
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do_sete(env, syndrome, mtedesc, set_step, false, GETPC());
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}
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@ -117,3 +117,7 @@ DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64)
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DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG,
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noreturn, env, i64, i32, i32)
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DEF_HELPER_3(setp, void, env, i32, i32)
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DEF_HELPER_3(setm, void, env, i32, i32)
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DEF_HELPER_3(sete, void, env, i32, i32)
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@ -3962,6 +3962,55 @@ TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false)
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TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true)
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TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true)
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typedef void SetFn(TCGv_env, TCGv_i32, TCGv_i32);
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static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue, SetFn fn)
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{
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int memidx;
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uint32_t syndrome, desc = 0;
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/*
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* UNPREDICTABLE cases: we choose to UNDEF, which allows
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* us to pull this check before the CheckMOPSEnabled() test
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* (which we do in the helper function)
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*/
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if (a->rs == a->rn || a->rs == a->rd || a->rn == a->rd ||
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a->rd == 31 || a->rn == 31) {
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return false;
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}
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memidx = get_a64_user_mem_index(s, a->unpriv);
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/*
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* We pass option_a == true, matching our implementation;
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* we pass wrong_option == false: helper function may set that bit.
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*/
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syndrome = syn_mop(true, false, (a->nontemp << 1) | a->unpriv,
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is_epilogue, false, true, a->rd, a->rs, a->rn);
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if (s->mte_active[a->unpriv]) {
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/* We may need to do MTE tag checking, so assemble the descriptor */
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desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
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desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
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desc = FIELD_DP32(desc, MTEDESC, WRITE, true);
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/* SIZEM1 and ALIGN we leave 0 (byte write) */
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}
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/* The helper function always needs the memidx even with MTE disabled */
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desc = FIELD_DP32(desc, MTEDESC, MIDX, memidx);
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/*
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* The helper needs the register numbers, but since they're in
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* the syndrome anyway, we let it extract them from there rather
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* than passing in an extra three integer arguments.
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*/
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fn(cpu_env, tcg_constant_i32(syndrome), tcg_constant_i32(desc));
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return true;
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}
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TRANS_FEAT(SETP, aa64_mops, do_SET, a, false, gen_helper_setp)
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TRANS_FEAT(SETM, aa64_mops, do_SET, a, false, gen_helper_setm)
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TRANS_FEAT(SETE, aa64_mops, do_SET, a, true, gen_helper_sete)
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typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64);
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static bool gen_rri(DisasContext *s, arg_rri_sf *a,
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|
|
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Loading…
Reference in New Issue