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hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit 

v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-11-19 21:56:11 +00:00
parent fe6fa228a7
commit 0e83f905fb
2 changed files with 20 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hw/intc/armv7m_nvic.c
View File

@ -1095,8 +1095,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
} }
return cpu->env.v7m.scr[attrs.secure]; return cpu->env.v7m.scr[attrs.secure];
case 0xd14: /* Configuration Control. */ case 0xd14: /* Configuration Control. */
/* The BFHFNMIGN bit is the only non-banked bit; we /*
* keep it in the non-secure copy of the register. * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
* and TRD (stored in the S copy of the register)
*/ */
val = cpu->env.v7m.ccr[attrs.secure]; val = cpu->env.v7m.ccr[attrs.secure];
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
@ -1639,17 +1640,25 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
cpu->env.v7m.scr[attrs.secure] = value; cpu->env.v7m.scr[attrs.secure] = value;
break; break;
case 0xd14: /* Configuration Control. */ case 0xd14: /* Configuration Control. */
{
uint32_t mask;
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset; goto bad_offset;
} }
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
value &= (R_V7M_CCR_STKALIGN_MASK | mask = R_V7M_CCR_STKALIGN_MASK |
R_V7M_CCR_BFHFNMIGN_MASK | R_V7M_CCR_BFHFNMIGN_MASK |
R_V7M_CCR_DIV_0_TRP_MASK | R_V7M_CCR_DIV_0_TRP_MASK |
R_V7M_CCR_UNALIGN_TRP_MASK | R_V7M_CCR_UNALIGN_TRP_MASK |
R_V7M_CCR_USERSETMPEND_MASK | R_V7M_CCR_USERSETMPEND_MASK |
R_V7M_CCR_NONBASETHRDENA_MASK); R_V7M_CCR_NONBASETHRDENA_MASK;
if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
/* TRD is always RAZ/WI from NS */
mask |= R_V7M_CCR_TRD_MASK;
}
value &= mask;
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
@ -1666,6 +1675,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
cpu->env.v7m.ccr[attrs.secure] = value; cpu->env.v7m.ccr[attrs.secure] = value;
break; break;
}
case 0xd24: /* System Handler Control and State (SHCSR) */ case 0xd24: /* System Handler Control and State (SHCSR) */
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
goto bad_offset; goto bad_offset;

2
target/arm/cpu.h
View File

@ -1611,6 +1611,8 @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, DC, 16, 1)
FIELD(V7M_CCR, IC, 17, 1) FIELD(V7M_CCR, IC, 17, 1)
FIELD(V7M_CCR, BP, 18, 1) FIELD(V7M_CCR, BP, 18, 1)
FIELD(V7M_CCR, LOB, 19, 1)
FIELD(V7M_CCR, TRD, 20, 1)
/* V7M SCR bits */ /* V7M SCR bits */
FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)