mirror of https://github.com/xemu-project/xemu.git
hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()
Merge common code shared between write_bootloader() and write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-12-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
9f911a2527
commit
0e45355c5c
155
hw/mips/malta.c
155
hw/mips/malta.c
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@ -616,11 +616,64 @@ static void network_init(PCIBus *pci_bus)
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}
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}
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}
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}
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static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
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uint64_t kernel_entry)
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{
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/* Bus endianess is always reversed */
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#if TARGET_BIG_ENDIAN
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#define cpu_to_gt32 cpu_to_le32
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#else
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#define cpu_to_gt32 cpu_to_be32
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#endif
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/* setup MEM-to-PCI0 mapping as done by YAMON */
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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bl_gen_write_u32(p, /* GT_ISD */
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cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
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cpu_to_gt32(0x1be00000 << 3));
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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bl_gen_write_u32(p, /* GT_PCI0IOLD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
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cpu_to_gt32(0x18000000 << 3));
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bl_gen_write_u32(p, /* GT_PCI0IOHD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
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cpu_to_gt32(0x08000000 << 3));
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/* setup PCI0 mem windows */
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bl_gen_write_u32(p, /* GT_PCI0M0LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
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cpu_to_gt32(0x10000000 << 3));
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bl_gen_write_u32(p, /* GT_PCI0M0HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
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cpu_to_gt32(0x07e00000 << 3));
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bl_gen_write_u32(p, /* GT_PCI0M1LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
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cpu_to_gt32(0x18200000 << 3));
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bl_gen_write_u32(p, /* GT_PCI0M1HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
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cpu_to_gt32(0x0bc00000 << 3));
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#undef cpu_to_gt32
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bl_gen_jump_kernel(p,
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true, ENVP_VADDR - 64,
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/*
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* If semihosting is used, arguments have already
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* been passed, so we preserve $a0.
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*/
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!semihosting_get_argc(), 2,
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true, ENVP_VADDR,
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true, ENVP_VADDR + 8,
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true, loaderparams.ram_low_size,
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kernel_entry);
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}
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static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
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static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
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uint64_t kernel_entry)
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uint64_t kernel_entry)
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{
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{
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uint16_t *p;
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uint16_t *p;
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void *v;
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/* Small bootloader */
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/* Small bootloader */
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p = (uint16_t *)base;
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p = (uint16_t *)base;
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@ -644,55 +697,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
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/* to_here: */
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/* to_here: */
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#if TARGET_BIG_ENDIAN
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bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
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#define cpu_to_gt32 cpu_to_le32
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#else
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#define cpu_to_gt32 cpu_to_be32
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#endif
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v = p;
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/* setup MEM-to-PCI0 mapping as done by YAMON */
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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bl_gen_write_u32(&v, /* GT_ISD */
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cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
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cpu_to_gt32(0x1be00000 << 3));
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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bl_gen_write_u32(&v, /* GT_PCI0IOLD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
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cpu_to_gt32(0x18000000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0IOHD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
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cpu_to_gt32(0x08000000 << 3));
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/* setup PCI0 mem windows */
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bl_gen_write_u32(&v, /* GT_PCI0M0LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
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cpu_to_gt32(0x10000000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M0HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
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cpu_to_gt32(0x07e00000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M1LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
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cpu_to_gt32(0x18200000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M1HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
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cpu_to_gt32(0x0bc00000 << 3));
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#undef cpu_to_gt32
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bl_gen_jump_kernel(&v,
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true, ENVP_VADDR - 64,
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/*
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* If semihosting is used, arguments have already been
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* passed, so we preserve $a0.
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*/
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!semihosting_get_argc(), 2,
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true, ENVP_VADDR,
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true, ENVP_VADDR + 8,
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true, loaderparams.ram_low_size,
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kernel_entry);
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}
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}
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/*
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/*
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@ -758,55 +763,8 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
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*
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*
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*/
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*/
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/* Bus endianess is always reversed */
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#if TARGET_BIG_ENDIAN
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#define cpu_to_gt32 cpu_to_le32
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#else
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#define cpu_to_gt32 cpu_to_be32
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#endif
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v = p;
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v = p;
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bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry);
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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bl_gen_write_u32(&v, /* GT_ISD */
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cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
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cpu_to_gt32(0x1be00000 << 3));
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/* setup MEM-to-PCI0 mapping */
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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bl_gen_write_u32(&v, /* GT_PCI0IOLD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
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cpu_to_gt32(0x18000000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0IOHD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
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cpu_to_gt32(0x08000000 << 3));
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/* setup PCI0 mem windows */
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bl_gen_write_u32(&v, /* GT_PCI0M0LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
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cpu_to_gt32(0x10000000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M0HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
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cpu_to_gt32(0x07e00000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M1LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
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cpu_to_gt32(0x18200000 << 3));
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bl_gen_write_u32(&v, /* GT_PCI0M1HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
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cpu_to_gt32(0x0bc00000 << 3));
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#undef cpu_to_gt32
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bl_gen_jump_kernel(&v,
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true, ENVP_VADDR - 64,
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/*
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* If semihosting is used, arguments have already been
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* passed, so we preserve $a0.
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*/
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!semihosting_get_argc(), 2,
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true, ENVP_VADDR,
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true, ENVP_VADDR + 8,
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true, loaderparams.ram_low_size,
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kernel_entry);
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p = v;
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p = v;
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/* YAMON subroutines */
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/* YAMON subroutines */
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@ -851,7 +809,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
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stl_p(p++, 0x00000000); /* nop */
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stl_p(p++, 0x00000000); /* nop */
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stl_p(p++, 0x03e00009); /* jalr ra */
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stl_p(p++, 0x03e00009); /* jalr ra */
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stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
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stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
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}
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}
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static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
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static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
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