From 0dbf6dc5766837c3d398c2d9f1d1695f4782fd77 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 30 Jun 2022 09:21:13 +0200 Subject: [PATCH] aspeed/hace: Accumulative mode supported MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While the HMAC mode is not modelled, the accumulative mode is. Accumulative mode is enabled by setting one of the bits in the HMAC engine command mode part of the register, so fix the unimplemented check to only look at the upper of the two bits. Fixes: 5cd7d8564a8b ("aspeed/hace: Support AST2600 HACE") Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Message-Id: <20220627100816.125956-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater --- hw/misc/aspeed_hace.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 731234b78c..ac21be306c 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -338,10 +338,10 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, int algo; data &= ahc->hash_mask; - if ((data & HASH_HMAC_MASK)) { + if ((data & HASH_DIGEST_HMAC)) { qemu_log_mask(LOG_UNIMP, - "%s: HMAC engine command mode %"PRIx64" not implemented\n", - __func__, (data & HASH_HMAC_MASK) >> 8); + "%s: HMAC mode not implemented\n", + __func__); } if (data & BIT(1)) { qemu_log_mask(LOG_UNIMP,