From 0d4046833ba44c5f29e5dcce2dde0a6202225e59 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 13 Dec 2012 16:12:03 +0000 Subject: [PATCH] openpic: BRR1 is not a CPU-specific register. It's in the address range that normally contains a magic redirection to the CPU-specific region of the curretn CPU, but it isn't actually a per-CPU register. On real hardware BRR1 shows up only at 0x40000, not at 0x60000 or other non-magic per-CPU areas. Plus, this makes it possible to read the register on the QEMU command line with "xp". Signed-off-by: Scott Wood Signed-off-by: Alexander Graf --- hw/openpic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index f0877fae5e..337dbf5a44 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -587,6 +587,8 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) retval = 0x00000000; break; case 0x00: /* Block Revision Register1 (BRR1) */ + retval = opp->brr1; + break; case 0x40: case 0x50: case 0x60: @@ -878,9 +880,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, dst = &opp->dst[idx]; addr &= 0xFF0; switch (addr) { - case 0x00: /* Block Revision Register1 (BRR1) */ - retval = opp->brr1; - break; case 0x80: /* PCTP */ retval = dst->pctp; break;