From 0ca0cc251d1b00ff1d2bd457b54b1426f4fab299 Mon Sep 17 00:00:00 2001 From: espes Date: Sun, 21 Jun 2015 01:41:32 +1000 Subject: [PATCH] build fixes --- hw/audio/ac97.c | 11 +++++------ hw/audio/ac97_int.h | 4 ++-- hw/xbox/chihiro.c | 3 ++- hw/xbox/mcpx_aci.c | 4 +++- hw/xbox/mcpx_apu.c | 15 +++++++++------ hw/xbox/nv2a.c | 32 +++++++++++++++++--------------- hw/xbox/nvnet.c | 2 ++ hw/xbox/xbox.c | 3 +-- 8 files changed, 41 insertions(+), 33 deletions(-) diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c index 2eb0e62764..60e4d0caa7 100644 --- a/hw/audio/ac97.c +++ b/hw/audio/ac97.c @@ -248,13 +248,12 @@ static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr) if (level) { s->glob_sta |= masks[r - s->bm_regs]; dolog ("set irq level=1\n"); - qemu_set_irq (s->irq, 1); + pci_irq_assert(s->pci_dev); } else { s->glob_sta &= ~masks[r - s->bm_regs]; dolog ("set irq level=0\n"); - qemu_set_irq (s->irq, 0); - pci_irq_deassert(&s->dev); + pci_irq_deassert(s->pci_dev); } } @@ -1280,10 +1279,10 @@ static void ac97_on_reset (void *opaque) } void ac97_common_init (AC97LinkState *s, - qemu_irq irq, + PCIDevice* pci_dev, AddressSpace *as) { - s->irq = irq; + s->pci_dev = pci_dev; s->as = as; qemu_register_reset (ac97_on_reset, s); @@ -1399,7 +1398,7 @@ static int ac97_initfn (PCIDevice *dev) pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam); pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm); - ac97_common_init(&s->state, s->dev.irq[0], pci_get_address_space(&s->dev)); + ac97_common_init(&s->state, &s->dev, pci_get_address_space(&s->dev)); return 0; } diff --git a/hw/audio/ac97_int.h b/hw/audio/ac97_int.h index bce9ebe6b6..3996c228f4 100644 --- a/hw/audio/ac97_int.h +++ b/hw/audio/ac97_int.h @@ -52,7 +52,7 @@ typedef struct AC97BusMasterRegs { } AC97BusMasterRegs; typedef struct AC97LinkState { - qemu_irq irq; + PCIDevice *pci_dev; AddressSpace *as; QEMUSoundCard card; @@ -72,7 +72,7 @@ typedef struct AC97LinkState { } AC97LinkState; void ac97_common_init (AC97LinkState *s, - qemu_irq irq, + PCIDevice *pci_dev, AddressSpace *as); diff --git a/hw/xbox/chihiro.c b/hw/xbox/chihiro.c index 4cf955b420..8c5d0c4023 100644 --- a/hw/xbox/chihiro.c +++ b/hw/xbox/chihiro.c @@ -18,6 +18,7 @@ */ #include "hw/hw.h" +#include "hw/i386/pc.h" #include "hw/boards.h" #include "hw/ide.h" #include "hw/loader.h" @@ -276,7 +277,7 @@ static QEMUMachine chihiro_machine = { .no_floppy = 1, .no_cdrom = 1, .no_sdcard = 1, - DEFAULT_MACHINE_OPTIONS + PC_DEFAULT_MACHINE_OPTIONS }; static void chihiro_machine_init(void) { diff --git a/hw/xbox/mcpx_aci.c b/hw/xbox/mcpx_aci.c index 3253c4038f..850182824c 100644 --- a/hw/xbox/mcpx_aci.c +++ b/hw/xbox/mcpx_aci.c @@ -42,6 +42,8 @@ static int mcpx_aci_initfn(PCIDevice *dev) { MCPXACIState *d = MCPX_ACI_DEVICE(dev); + dev->config[PCI_INTERRUPT_PIN] = 0x01; + //mmio memory_region_init(&d->mmio, OBJECT(dev), "mcpx-aci-mmio", 0x1000); @@ -64,7 +66,7 @@ static int mcpx_aci_initfn(PCIDevice *dev) pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); - ac97_common_init(&d->ac97, dev->irq[0], pci_get_address_space(&d->dev)); + ac97_common_init(&d->ac97, &d->dev, pci_get_address_space(&d->dev)); return 0; } diff --git a/hw/xbox/mcpx_apu.c b/hw/xbox/mcpx_apu.c index 1fe93cd706..84a6f8ec58 100644 --- a/hw/xbox/mcpx_apu.c +++ b/hw/xbox/mcpx_apu.c @@ -187,11 +187,11 @@ static void update_irq(MCPXAPUState *d) d->regs[NV_PAPU_ISTS] |= NV_PAPU_ISTS_GINTSTS; MCPX_DPRINTF("mcpx irq raise\n"); - qemu_irq_raise(d->dev.irq[0]); + pci_irq_assert(&d->dev); } else { d->regs[NV_PAPU_ISTS] &= ~NV_PAPU_ISTS_GINTSTS; MCPX_DPRINTF("mcpx irq lower\n"); - qemu_irq_lower(d->dev.irq[0]); + pci_irq_deassert(&d->dev); } } @@ -228,9 +228,10 @@ static void mcpx_apu_write(void *opaque, hwaddr addr, case NV_PAPU_SECTL: if ( ((val & NV_PAPU_SECTL_XCNTMODE) >> 3) == NV_PAPU_SECTL_XCNTMODE_OFF) { - qemu_del_timer(d->se.frame_timer); + timer_del(d->se.frame_timer); } else { - qemu_mod_timer(d->se.frame_timer, qemu_get_clock_ms(vm_clock) + 10); + timer_mod(d->se.frame_timer, + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10); } d->regs[addr] = val; break; @@ -438,7 +439,7 @@ static const MemoryRegionOps gp_ops = { static void se_frame(void *opaque) { MCPXAPUState *d = opaque; - qemu_mod_timer(d->se.frame_timer, qemu_get_clock_ms(vm_clock) + 10); + timer_mod(d->se.frame_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 10); MCPX_DPRINTF("mcpx frame ping\n"); int list; for (list=0; list < 3; list++) { @@ -477,6 +478,8 @@ static int mcpx_apu_initfn(PCIDevice *dev) { MCPXAPUState *d = MCPX_APU_DEVICE(dev); + dev->config[PCI_INTERRUPT_PIN] = 0x01; + memory_region_init_io(&d->mmio, OBJECT(dev), &mcpx_apu_mmio_ops, d, "mcpx-apu-mmio", 0x80000); @@ -491,7 +494,7 @@ static int mcpx_apu_initfn(PCIDevice *dev) pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); - d->se.frame_timer = qemu_new_timer_ms(vm_clock, se_frame, d); + d->se.frame_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, se_frame, d); d->gp.dsp = dsp_init(d, gp_scratch_rw); diff --git a/hw/xbox/nv2a.c b/hw/xbox/nv2a.c index 9d1f29e2d4..58a9fa8426 100644 --- a/hw/xbox/nv2a.c +++ b/hw/xbox/nv2a.c @@ -1160,9 +1160,9 @@ static void update_irq(NV2AState *d) } if (d->pmc.pending_interrupts && d->pmc.enabled_interrupts) { - qemu_irq_raise(d->dev.irq[0]); + pci_irq_assert(&d->dev); } else { - qemu_irq_lower(d->dev.irq[0]); + pci_irq_deassert(&d->dev); } } @@ -1195,8 +1195,8 @@ static RAMHTEntry ramht_lookup(NV2AState *d, uint32_t handle) entry_ptr = d->ramin_ptr + d->pfifo.ramht_address + hash * 8; - entry_handle = le32_to_cpupu((uint32_t*)entry_ptr); - entry_context = le32_to_cpupu((uint32_t*)(entry_ptr + 4)); + entry_handle = ldl_le_p((uint32_t*)entry_ptr); + entry_context = ldl_le_p((uint32_t*)(entry_ptr + 4)); return (RAMHTEntry){ .handle = entry_handle, @@ -1212,9 +1212,9 @@ static DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address) assert(dma_obj_address < memory_region_size(&d->ramin)); uint32_t *dma_obj = (uint32_t*)(d->ramin_ptr + dma_obj_address); - uint32_t flags = le32_to_cpupu(dma_obj); - uint32_t limit = le32_to_cpupu(dma_obj + 1); - uint32_t frame = le32_to_cpupu(dma_obj + 2); + uint32_t flags = ldl_le_p(dma_obj); + uint32_t limit = ldl_le_p(dma_obj + 1); + uint32_t frame = ldl_le_p(dma_obj + 2); return (DMAObject){ .dma_class = GET_MASK(flags, NV_DMA_CLASS), @@ -1248,9 +1248,9 @@ static void load_graphics_object(NV2AState *d, hwaddr instance_address, obj_ptr = d->ramin_ptr + instance_address; - switch1 = le32_to_cpupu((uint32_t*)obj_ptr); - switch2 = le32_to_cpupu((uint32_t*)(obj_ptr+4)); - switch3 = le32_to_cpupu((uint32_t*)(obj_ptr+8)); + switch1 = ldl_le_p((uint32_t*)obj_ptr); + switch2 = ldl_le_p((uint32_t*)(obj_ptr+4)); + switch3 = ldl_le_p((uint32_t*)(obj_ptr+8)); obj->graphics_class = switch1 & NV_PGRAPH_CTX_SWITCH1_GRCLASS; @@ -1319,7 +1319,7 @@ static void pgraph_bind_converted_vertex_attributes(NV2AState *d, switch (attribute->format) { case NV097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_CMP: - r11g11b10f_to_float3(le32_to_cpupu((uint32_t*)in), + r11g11b10f_to_float3(ldl_le_p((uint32_t*)in), (float*)out); break; default: @@ -2873,7 +2873,7 @@ static void pgraph_method(NV2AState *d, assert(kelvin->semaphore_offset < semaphore_dma_len); semaphore_data += kelvin->semaphore_offset; - cpu_to_le32wu((uint32_t*)semaphore_data, parameter); + stl_le_p((uint32_t*)semaphore_data, parameter); //qemu_mutex_lock(&d->pgraph.lock); //qemu_mutex_unlock_iothread(); @@ -3187,7 +3187,7 @@ static void pfifo_run_pusher(NV2AState *d) { break; } - word = le32_to_cpupu((uint32_t*)(dma + control->dma_get)); + word = ldl_le_p((uint32_t*)(dma + control->dma_get)); control->dma_get += 4; if (state->method_count) { @@ -3690,7 +3690,7 @@ static void pvideo_write(void *opaque, hwaddr addr, /* PIMTER - time measurement and time-based alarms */ static uint64_t ptimer_get_clock(NV2AState *d) { - return muldiv64(qemu_get_clock_ns(vm_clock), + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), d->pramdac.core_clock_freq * d->ptimer.numerator, get_ticks_per_sec() * d->ptimer.denominator); } @@ -3997,7 +3997,7 @@ static void pgraph_write(void *opaque, hwaddr addr, d->pgraph.channel_id, d->pgraph.context_address); uint8_t *context_ptr = d->ramin_ptr + d->pgraph.context_address; - uint32_t context_user = le32_to_cpupu((uint32_t*)context_ptr); + uint32_t context_user = ldl_le_p((uint32_t*)context_ptr); NV2A_DPRINTF(" - CTX_USER = 0x%x\n", context_user); @@ -4721,6 +4721,8 @@ static int nv2a_initfn(PCIDevice *dev) d = NV2A_DEVICE(dev); + dev->config[PCI_INTERRUPT_PIN] = 0x01; + d->pcrtc.start = 0; d->pramdac.core_clock_coeff = 0x00011c01; /* 189MHz...? */ diff --git a/hw/xbox/nvnet.c b/hw/xbox/nvnet.c index 9708a2a28e..ee95704192 100644 --- a/hw/xbox/nvnet.c +++ b/hw/xbox/nvnet.c @@ -78,6 +78,8 @@ static int nvnet_initfn(PCIDevice *dev) { NVNetState *d = NVNET_DEVICE(dev); + dev->config[PCI_INTERRUPT_PIN] = 0x01; + memory_region_init_io(&d->mmio, OBJECT(dev), &nvnet_mmio_ops, d, "nvnet-mmio", MMIO_SIZE); pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); diff --git a/hw/xbox/xbox.c b/hw/xbox/xbox.c index fba780f32e..8d7d696571 100644 --- a/hw/xbox/xbox.c +++ b/hw/xbox/xbox.c @@ -125,7 +125,6 @@ void xbox_init_common(QEMUMachineInitArgs *args, int i; ram_addr_t ram_size = args->ram_size; const char *cpu_model = args->cpu_model; - const char *boot_device = args->boot_device; PCIBus *host_bus; ISABus *isa_bus; @@ -340,7 +339,7 @@ static QEMUMachine xbox_machine = { .no_floppy = 1, .no_cdrom = 1, .no_sdcard = 1, - DEFAULT_MACHINE_OPTIONS + PC_DEFAULT_MACHINE_OPTIONS }; static void xbox_machine_init(void) {