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target/mips: Convert MSA ELM instruction format to decodetree 

Convert instructions with an immediate element index
and data format df/n to decodetree.

Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-25-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 17:16:45 +02:00
parent 0a086d2e80
commit 0a510c934c
2 changed files with 52 additions and 13 deletions
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8
target/mips/tcg/msa.decode
View File

@ -18,7 +18,10 @@
&msa_ldi df wd sa
&msa_i df wd ws sa
&msa_bit df wd ws m
&msa_elm_df df wd ws n
%elm_df 16:6 !function=elm_df
%elm_n 16:6 !function=elm_n
%bit_df 16:7 !function=bit_df
%bit_m 16:7 !function=bit_m
%2r_df_w 16:1 !function=plus_2
@ -29,6 +32,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
@ -161,6 +165,10 @@ BNZ 010001 111 .. ..... ................ @bz
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w

57
target/mips/tcg/msa_translate.c
View File

@ -17,6 +17,8 @@
#include "fpu_helper.h"
#include "internal.h"
static int elm_n(DisasContext *ctx, int x);
static int elm_df(DisasContext *ctx, int x);
static int bit_m(DisasContext *ctx, int x);
static int bit_df(DisasContext *ctx, int x);
@ -42,15 +44,12 @@ enum {
enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@ -107,6 +106,24 @@ static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s)
return -1;
}
static const struct dfe df_elm[] = {
/* Table 3.26 ELM Instruction Format */
[DF_BYTE] = {4, 2, 0b00},
[DF_HALF] = {3, 3, 0b100},
[DF_WORD] = {2, 4, 0b1100},
[DF_DOUBLE] = {1, 5, 0b11100}
};
static int elm_n(DisasContext *ctx, int x)
{
return df_extract_val(ctx, x, df_elm);
}
static int elm_df(DisasContext *ctx, int x)
{
return df_extract_df(ctx, x, df_elm);
}
static const struct dfe df_bit[] = {
/* Table 3.28 BIT Instruction Format */
[DF_BYTE] = {3, 4, 0b1110},
@ -551,6 +568,30 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free_i32(tsr);
}
static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a,
gen_helper_piiii *gen_msa_elm_df)
{
if (a->df < 0) {
return false;
}
if (!check_msa_enabled(ctx)) {
return true;
}
gen_msa_elm_df(cpu_env,
tcg_constant_i32(a->df),
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->n));
return true;
}
TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df);
TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df);
TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df);
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@ -560,18 +601,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_SLDI_df:
gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
break;
case OPC_SPLATI_df:
gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
break;
case OPC_INSVE_df:
gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
break;
case OPC_COPY_S_df:
case OPC_COPY_U_df:
case OPC_INSERT_df: