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target/tricore: Use setcondi instead of explicit allocation 

This removes the only use of temp.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-26 12:32:01 -10:00
parent 5c48ad758d
commit 0a47678626
1 changed files with 2 additions and 5 deletions
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7
target/tricore/translate.c
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@ -3514,17 +3514,14 @@ static void decode_sr_accu(DisasContext *ctx)
{ {
uint32_t op2; uint32_t op2;
uint32_t r1; uint32_t r1;
TCGv temp;
r1 = MASK_OP_SR_S1D(ctx->opcode); r1 = MASK_OP_SR_S1D(ctx->opcode);
op2 = MASK_OP_SR_OP2(ctx->opcode); op2 = MASK_OP_SR_OP2(ctx->opcode);
switch (op2) { switch (op2) {
case OPC2_16_SR_RSUB: case OPC2_16_SR_RSUB:
/* overflow only if r1 = -0x80000000 */ /* calc V bit -- overflow only if r1 = -0x80000000 */
temp = tcg_const_i32(-0x80000000); tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
/* calc V bit */
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
/* calc SV bit */ /* calc SV bit */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);