diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index e6bffb9e1a..6198ec1035 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -191,7 +191,7 @@ static void ref405ep_init(MachineState *machine) bios_size = 8 * MiB; pflash_cfi02_register((uint32_t)(-bios_size), "ef405ep.bios", bios_size, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + blk_by_legacy_dinfo(dinfo), 64 * KiB, 1, 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); @@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine) bios_size = 2 * MiB; pflash_cfi02_register(0xFFE00000, "taihu_405ep.bios", bios_size, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + blk_by_legacy_dinfo(dinfo), 64 * KiB, 1, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); @@ -494,7 +494,7 @@ static void taihu_405ep_init(MachineState *machine) if (dinfo) { bios_size = 32 * MiB; pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + blk_by_legacy_dinfo(dinfo), 64 * KiB, 1, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 323fcef4aa..a4a540f43d 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -243,6 +243,14 @@ struct rtas_event_log_v6_mc { #define RTAS_LOG_V6_MC_TLB_PARITY 1 #define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 #define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 +/* + * Per PAPR, + * For UE error type, set bit 1 of sub_err_type to indicate effective addr is + * provided. For other error types (SLB/ERAT/TLB), set bit 0 to indicate + * same. + */ +#define RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED 0x40 +#define RTAS_LOG_V6_MC_EA_ADDR_PROVIDED 0x80 uint8_t reserved_1[6]; uint64_t effective_address; uint64_t logical_address; @@ -726,6 +734,22 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id); } +static void spapr_mc_set_ea_provided_flag(struct mc_extended_log *ext_elog) +{ + switch (ext_elog->mc.error_type) { + case RTAS_LOG_V6_MC_TYPE_UE: + ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED; + break; + case RTAS_LOG_V6_MC_TYPE_SLB: + case RTAS_LOG_V6_MC_TYPE_ERAT: + case RTAS_LOG_V6_MC_TYPE_TLB: + ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_EA_ADDR_PROVIDED; + break; + default: + break; + } +} + static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, struct mc_extended_log *ext_elog) { @@ -751,6 +775,7 @@ static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype; if (mc_derror_table[i].dar_valid) { ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]); + spapr_mc_set_ea_provided_flag(ext_elog); } summary |= mc_derror_table[i].initiator @@ -769,6 +794,7 @@ static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype; if (mc_ierror_table[i].nip_valid) { ext_elog->mc.effective_address = cpu_to_be64(env->nip); + spapr_mc_set_ea_provided_flag(ext_elog); } summary |= mc_ierror_table[i].initiator diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 40c86e91eb..0d50fc9117 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1726,6 +1726,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, } ov5_guest = spapr_ovec_parse_vector(ov_table, 5); if (!ov5_guest) { + spapr_ovec_cleanup(ov1_guest); warn_report("guest didn't provide option vector 5"); return H_PARAMETER; } diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 0c4e7ba54c..ecd99736b7 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -567,10 +567,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->nip = tswapl(handler->entry); env->gpr[2] = tswapl(handler->toc); } else { - /* ELFv2 PPC64 function pointers are entry points, but R12 - * must also be set */ - env->nip = tswapl((target_ulong) ka->_sa_handler); - env->gpr[12] = env->nip; + /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */ + env->gpr[12] = env->nip = ka->_sa_handler; } #else env->nip = (target_ulong) ka->_sa_handler; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cfb4c07085..a95c010391 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -614,7 +614,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_2(load_slb_esid, tl, env, tl) DEF_HELPER_2(load_slb_vsid, tl, env, tl) DEF_HELPER_2(find_slb_vsid, tl, env, tl) -DEF_HELPER_FLAGS_1(slbia, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl) #endif diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 34f6009b1e..e5baabf0e1 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -95,24 +95,75 @@ void dump_slb(PowerPCCPU *cpu) } } -void helper_slbia(CPUPPCState *env) +void helper_slbia(CPUPPCState *env, uint32_t ih) { PowerPCCPU *cpu = env_archcpu(env); + int starting_entry; int n; - /* XXX: Warning: slbia never invalidates the first segment */ - for (n = 1; n < cpu->hash64_opts->slb_size; n++) { + /* + * slbia must always flush all TLB (which is equivalent to ERAT in ppc + * architecture). Matching on SLB_ESID_V is not good enough, because slbmte + * can overwrite a valid SLB without flushing its lookaside information. + * + * It would be possible to keep the TLB in synch with the SLB by flushing + * when a valid entry is overwritten by slbmte, and therefore slbia would + * not have to flush unless it evicts a valid SLB entry. However it is + * expected that slbmte is more common than slbia, and slbia is usually + * going to evict valid SLB entries, so that tradeoff is unlikely to be a + * good one. + * + * ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate + * the same SLB entries (everything but entry 0), but differ in what + * "lookaside information" is invalidated. TCG can ignore this and flush + * everything. + * + * ISA v3.0 introduced additional values 3,4,7, which change what SLBs are + * invalidated. + */ + + env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; + + starting_entry = 1; /* default for IH=0,1,2,6 */ + + if (env->mmu_model == POWERPC_MMU_3_00) { + switch (ih) { + case 0x7: + /* invalidate no SLBs, but all lookaside information */ + return; + + case 0x3: + case 0x4: + /* also considers SLB entry 0 */ + starting_entry = 0; + break; + + case 0x5: + /* treat undefined values as ih==0, and warn */ + qemu_log_mask(LOG_GUEST_ERROR, + "slbia undefined IH field %u.\n", ih); + break; + + default: + /* 0,1,2,6 */ + break; + } + } + + for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) { ppc_slb_t *slb = &env->slb[n]; - if (slb->esid & SLB_ESID_V) { - slb->esid &= ~SLB_ESID_V; - /* - * XXX: given the fact that segment size is 256 MB or 1TB, - * and we still don't have a tlb_flush_mask(env, n, mask) - * in QEMU, we just invalidate all TLBs - */ - env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; + if (!(slb->esid & SLB_ESID_V)) { + continue; } + if (env->mmu_model == POWERPC_MMU_3_00) { + if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) { + /* preserves entries with a class value of 0 */ + continue; + } + } + + slb->esid &= ~SLB_ESID_V; } } diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 703bd9ed18..d16360ab66 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -21,6 +21,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "qemu/log.h" +#include "qemu/main-loop.h" /*****************************************************************************/ /* SPR accesses */ @@ -167,13 +168,19 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL, GETPC()); - } else if (unlikely(ppc_dcr_read(env->dcr_env, - (uint32_t)dcrn, &val) != 0)) { - qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", - (uint32_t)dcrn, (uint32_t)dcrn); - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL | - POWERPC_EXCP_PRIV_REG, GETPC()); + } else { + int ret; + + qemu_mutex_lock_iothread(); + ret = ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val); + qemu_mutex_unlock_iothread(); + if (unlikely(ret != 0)) { + qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", + (uint32_t)dcrn, (uint32_t)dcrn); + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | + POWERPC_EXCP_PRIV_REG, GETPC()); + } } return val; } @@ -185,12 +192,17 @@ void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL, GETPC()); - } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, - (uint32_t)val) != 0)) { - qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", - (uint32_t)dcrn, (uint32_t)dcrn); - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL | - POWERPC_EXCP_PRIV_REG, GETPC()); + } else { + int ret; + qemu_mutex_lock_iothread(); + ret = ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val); + qemu_mutex_unlock_iothread(); + if (unlikely(ret != 0)) { + qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", + (uint32_t)dcrn, (uint32_t)dcrn); + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | + POWERPC_EXCP_PRIV_REG, GETPC()); + } } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 127c82a24e..b207fb5386 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4997,9 +4997,12 @@ static void gen_slbia(DisasContext *ctx) #if defined(CONFIG_USER_ONLY) GEN_PRIV; #else + uint32_t ih = (ctx->opcode >> 21) & 0x7; + TCGv_i32 t0 = tcg_const_i32(ih); + CHK_SV; - gen_helper_slbia(cpu_env); + gen_helper_slbia(cpu_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ }