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target/arm: Split out gengvec.c 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240524232121.284515-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-24 16:20:21 -07:00 committed by Peter Maydell
parent 5d874e5da2
commit 09a52d854a
4 changed files with 1618 additions and 1588 deletions
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1612
target/arm/tcg/gengvec.c Normal file
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target/arm/tcg/meson.build
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@ -24,6 +24,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
arm_ss.add(files(
'cpu32.c',
'gengvec.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',

1588
target/arm/tcg/translate.c
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5
target/arm/tcg/translate.h
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@ -445,6 +445,11 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh);
void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh);
void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh);
void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh);
void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,