mirror of https://github.com/xemu-project/xemu.git
tcg-arm: Use TCGMemOp within qemu_ldst routines
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
8221a267fd
commit
099fcf2e36
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@ -1169,7 +1169,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
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containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int s_bits, int mem_index, bool is_load)
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TCGMemOp s_bits, int mem_index, bool is_load)
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{
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TCGReg base = TCG_AREG0;
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int cmp_off =
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@ -1240,7 +1240,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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/* Record the context of a call to the out of line helper code for the slow
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path for a load or store, so that we can later generate the correct
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helper code. */
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOp opc,
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int data_reg, int data_reg2, int addrlo_reg,
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int addrhi_reg, int mem_index,
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uint8_t *raddr, uint8_t *label_ptr)
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@ -1261,7 +1261,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGReg argreg, data_reg, data_reg2;
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int opc = lb->opc;
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TCGMemOp opc = lb->opc & MO_SSIZE;
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uintptr_t func;
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reloc_pc24(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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@ -1279,11 +1279,11 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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icache usage. For pre-armv6, use the signed helpers since we do
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not have a single insn sign-extend. */
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if (use_armv6_instructions) {
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func = (uintptr_t)qemu_ld_helpers[opc & 3];
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func = (uintptr_t)qemu_ld_helpers[opc & MO_SIZE];
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} else {
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func = (uintptr_t)qemu_ld_helpers[opc];
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if (opc & 4) {
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opc = 2;
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if (opc & MO_SIGN) {
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opc = MO_UL;
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}
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}
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tcg_out_call(s, func);
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@ -1291,16 +1291,16 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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data_reg = lb->datalo_reg;
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data_reg2 = lb->datahi_reg;
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switch (opc) {
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case 0 | 4:
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case MO_SB:
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tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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case 1 | 4:
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case MO_SW:
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tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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default:
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tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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case 3:
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case MO_Q:
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if (data_reg != TCG_REG_R1) {
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tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0);
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tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1);
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@ -1321,6 +1321,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGReg argreg, data_reg, data_reg2;
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TCGMemOp s_bits = lb->opc & MO_SIZE;
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reloc_pc24(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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@ -1334,17 +1335,18 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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data_reg = lb->datalo_reg;
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data_reg2 = lb->datahi_reg;
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switch (lb->opc) {
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case 0:
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switch (s_bits) {
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case MO_8:
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argreg = tcg_out_arg_reg8(s, argreg, data_reg);
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break;
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case 1:
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case MO_16:
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argreg = tcg_out_arg_reg16(s, argreg, data_reg);
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break;
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case 2:
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case MO_32:
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default:
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argreg = tcg_out_arg_reg32(s, argreg, data_reg);
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break;
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case 3:
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case MO_64:
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argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
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break;
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}
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@ -1353,32 +1355,27 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
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/* Tail-call to the helper, which will return to the fast path. */
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tcg_out_goto(s, COND_AL, (tcg_target_long) qemu_st_helpers[lb->opc & 3]);
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tcg_out_goto(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits]);
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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TCGMemOp bswap = opc & MO_BSWAP;
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TCGMemOp s_bits = opc & MO_SIZE;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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int mem_index;
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TCGReg addr_reg2, addend;
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uint8_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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data_reg = *args++;
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data_reg2 = (opc == 3 ? *args++ : 0);
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data_reg2 = (s_bits == MO_64 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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addend = tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits, mem_index, 1);
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@ -1387,20 +1384,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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label_ptr = s->code_ptr;
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tcg_out_bl_noaddr(s, COND_NE);
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switch (opc) {
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case 0:
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switch (opc & MO_SSIZE) {
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case MO_UB:
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tcg_out_ld8_r(s, COND_AL, data_reg, addr_reg, addend);
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break;
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case 0 | 4:
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case MO_SB:
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tcg_out_ld8s_r(s, COND_AL, data_reg, addr_reg, addend);
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break;
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case 1:
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case MO_UW:
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tcg_out_ld16u_r(s, COND_AL, data_reg, addr_reg, addend);
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if (bswap) {
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tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 1 | 4:
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case MO_SW:
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if (bswap) {
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tcg_out_ld16u_r(s, COND_AL, data_reg, addr_reg, addend);
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tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
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@ -1408,14 +1405,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_ld16s_r(s, COND_AL, data_reg, addr_reg, addend);
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}
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break;
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case 2:
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case MO_UL:
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default:
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tcg_out_ld32_r(s, COND_AL, data_reg, addr_reg, addend);
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 3:
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case MO_Q:
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{
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/* Be careful not to modify data_reg and data_reg2
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for the slow path below. */
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@ -1458,20 +1455,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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offset &= ~(0xff << i);
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}
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}
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switch (opc) {
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case 0:
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switch (opc & MO_SSIZE) {
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case MO_UB:
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tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
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break;
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case 0 | 4:
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case MO_SB:
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tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
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break;
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case 1:
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case MO_UW:
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tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
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if (bswap) {
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tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 1 | 4:
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case MO_SW:
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if (bswap) {
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tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
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tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
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@ -1479,14 +1476,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
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}
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break;
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case 2:
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case MO_UL:
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default:
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tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 3:
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case MO_Q:
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if (use_armv6_instructions && !bswap
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&& (data_reg & 1) == 0 && data_reg2 == data_reg + 1) {
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tcg_out_ldrd_8(s, COND_AL, data_reg, addr_reg, 0);
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@ -1509,12 +1506,13 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#endif
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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TCGMemOp bswap = opc & MO_BSWAP;
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TCGMemOp s_bits = opc & MO_SIZE;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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int mem_index;
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TCGReg addr_reg2, addend;
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uint8_t *label_ptr;
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#endif
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@ -1525,20 +1523,19 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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#endif
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data_reg = *args++;
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data_reg2 = (opc == 3 ? *args++ : 0);
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data_reg2 = (s_bits == MO_64 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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addend = tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits, mem_index, 0);
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switch (opc) {
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case 0:
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switch (s_bits) {
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case MO_8:
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tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, addend);
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break;
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case 1:
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case MO_16:
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if (bswap) {
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tcg_out_bswap16st(s, COND_EQ, TCG_REG_R0, data_reg);
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tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, addend);
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@ -1546,7 +1543,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, addend);
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}
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break;
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case 2:
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case MO_32:
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default:
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if (bswap) {
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tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
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@ -1555,7 +1552,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, addend);
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}
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break;
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case 3:
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case MO_64:
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if (bswap) {
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tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
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tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, addend, addr_reg);
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@ -1593,11 +1590,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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offset &= ~(0xff << i);
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}
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}
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switch (opc) {
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case 0:
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switch (s_bits) {
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case MO_8:
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tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
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break;
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case 1:
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case MO_16:
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if (bswap) {
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tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, data_reg);
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tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
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@ -1605,7 +1602,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
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}
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break;
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case 2:
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case MO_32:
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default:
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
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@ -1614,7 +1611,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
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}
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break;
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case 3:
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case MO_64:
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
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tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
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@ -1898,35 +1895,35 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_qemu_ld8u:
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tcg_out_qemu_ld(s, args, 0);
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tcg_out_qemu_ld(s, args, MO_UB);
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break;
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case INDEX_op_qemu_ld8s:
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tcg_out_qemu_ld(s, args, 0 | 4);
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tcg_out_qemu_ld(s, args, MO_SB);
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break;
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case INDEX_op_qemu_ld16u:
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tcg_out_qemu_ld(s, args, 1);
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tcg_out_qemu_ld(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_ld16s:
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tcg_out_qemu_ld(s, args, 1 | 4);
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tcg_out_qemu_ld(s, args, MO_TESW);
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break;
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case INDEX_op_qemu_ld32:
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tcg_out_qemu_ld(s, args, 2);
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tcg_out_qemu_ld(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_ld64:
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tcg_out_qemu_ld(s, args, 3);
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tcg_out_qemu_ld(s, args, MO_TEQ);
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break;
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case INDEX_op_qemu_st8:
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tcg_out_qemu_st(s, args, 0);
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tcg_out_qemu_st(s, args, MO_UB);
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break;
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case INDEX_op_qemu_st16:
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tcg_out_qemu_st(s, args, 1);
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tcg_out_qemu_st(s, args, MO_TEUW);
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break;
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case INDEX_op_qemu_st32:
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tcg_out_qemu_st(s, args, 2);
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tcg_out_qemu_st(s, args, MO_TEUL);
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break;
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case INDEX_op_qemu_st64:
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tcg_out_qemu_st(s, args, 3);
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tcg_out_qemu_st(s, args, MO_TEQ);
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break;
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case INDEX_op_bswap16_i32:
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