mirror of https://github.com/xemu-project/xemu.git
tcg/riscv: Support CPOP from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1511,6 +1511,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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}
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break;
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break;
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case INDEX_op_ctpop_i32:
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tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0);
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break;
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case INDEX_op_ctpop_i64:
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tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
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break;
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case INDEX_op_add2_i32:
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case INDEX_op_add2_i32:
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tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
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tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
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const_args[4], const_args[5], false, true);
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const_args[4], const_args[5], false, true);
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@ -1637,6 +1644,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_bswap16_i64:
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case INDEX_op_bswap16_i64:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64_i64:
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case INDEX_op_ctpop_i32:
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case INDEX_op_ctpop_i64:
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return C_O1_I1(r, r);
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return C_O1_I1(r, r);
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case INDEX_op_st8_i32:
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case INDEX_op_st8_i32:
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@ -127,7 +127,7 @@ extern bool have_zbb;
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 0
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#define TCG_TARGET_HAS_clz_i32 0
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 have_zbb
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#define TCG_TARGET_HAS_brcond2 1
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#define TCG_TARGET_HAS_brcond2 1
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#define TCG_TARGET_HAS_setcond2 1
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#define TCG_TARGET_HAS_setcond2 1
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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@ -161,7 +161,7 @@ extern bool have_zbb;
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_clz_i64 0
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#define TCG_TARGET_HAS_clz_i64 0
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 have_zbb
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 0
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