mirror of https://github.com/xemu-project/xemu.git
xbox: fix for the target_phys_addr_t -> hwaddr change
This commit is contained in:
espes
parent
156f9dd182
commit
0949deffaf
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@ -56,7 +56,7 @@ static void mcpx_pm_update_sci_gn(ACPIREGS *regs)
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#define MCPX_PMIO_PM_TMR 0x8
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static void mcpx_pm_ioport_write(void *opaque,
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target_phys_addr_t addr,
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hwaddr addr,
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uint64_t val, unsigned size)
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{
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MCPX_PMRegs *pm = opaque;
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@ -81,7 +81,7 @@ static void mcpx_pm_ioport_write(void *opaque,
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}
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static uint64_t mcpx_pm_ioport_read(void *opaque,
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target_phys_addr_t addr,
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hwaddr addr,
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unsigned size)
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{
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MCPX_PMRegs *pm = opaque;
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80
hw/nv2a.c
80
hw/nv2a.c
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@ -77,19 +77,19 @@ typedef struct NV2AState {
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MemoryRegion block_mmio[NV_NUM_BLOCKS];
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target_phys_addr_t crtc_start;
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hwaddr crtc_start;
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} NV2AState;
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static uint64_t nv2a_pmc_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PMC: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pmc_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pmc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PMC: [0x%llx] = 0x%02llx\n", addr, val);
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@ -97,12 +97,12 @@ static void nv2a_pmc_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pbus_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PBUS: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pbus_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pbus_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PBUS: [0x%llx] = 0x%02llx\n", addr, val);
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@ -110,12 +110,12 @@ static void nv2a_pbus_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pfifo_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PFIFO: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pfifo_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pfifo_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PFIFO: [0x%llx] = 0x%02llx\n", addr, val);
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@ -123,12 +123,12 @@ static void nv2a_pfifo_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_prma_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMA: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_prma_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_prma_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMA: [0x%llx] = 0x%02llx\n", addr, val);
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@ -136,12 +136,12 @@ static void nv2a_prma_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pvideo_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PVIDEO: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pvideo_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pvideo_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PVIDEO: [0x%llx] = 0x%02llx\n", addr, val);
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@ -149,12 +149,12 @@ static void nv2a_pvideo_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_ptimer_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PTIMER: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_ptimer_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_ptimer_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PTIMER: [0x%llx] = 0x%02llx\n", addr, val);
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@ -162,12 +162,12 @@ static void nv2a_ptimer_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pcounter_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PCOUNTER: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pcounter_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pcounter_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PCOUNTER: [0x%llx] = 0x%02llx\n", addr, val);
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@ -175,12 +175,12 @@ static void nv2a_pcounter_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pvpe_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PVPE: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pvpe_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pvpe_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PVPE: [0x%llx] = 0x%02llx\n", addr, val);
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@ -188,12 +188,12 @@ static void nv2a_pvpe_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_ptv_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PTV: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_ptv_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_ptv_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PTV: [0x%llx] = 0x%02llx\n", addr, val);
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@ -201,12 +201,12 @@ static void nv2a_ptv_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_prmfb_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMFB: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_prmfb_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_prmfb_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMFB: [0x%llx] = 0x%02llx\n", addr, val);
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@ -215,7 +215,7 @@ static void nv2a_prmfb_write(void *opaque, target_phys_addr_t addr,
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/* PRMVIO -aliases VGA sequencer and graphics controller registers */
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static uint64_t nv2a_prmvio_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2AState *d = opaque;
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uint64_t r = vga_ioport_read(&d->vga, addr);
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@ -223,7 +223,7 @@ static uint64_t nv2a_prmvio_read(void *opaque,
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NV2A_DPRINTF("nv2a PRMVIO: read [0x%llx] -> %llx\n", addr, r);
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return r;
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}
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static void nv2a_prmvio_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_prmvio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2AState *d = opaque;
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@ -236,12 +236,12 @@ static void nv2a_prmvio_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pstraps_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PSTRAPS: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pstraps_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pstraps_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PSTRAPS: [0x%llx] = 0x%02llx\n", addr, val);
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@ -249,12 +249,12 @@ static void nv2a_pstraps_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pgraph_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PGRAPH: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pgraph_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pgraph_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PGRAPH: [0x%llx] = 0x%02llx\n", addr, val);
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@ -262,7 +262,7 @@ static void nv2a_pgraph_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pcrtc_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2AState *d = opaque;
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uint64_t r = 0;
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@ -276,7 +276,7 @@ static uint64_t nv2a_pcrtc_read(void *opaque,
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NV2A_DPRINTF("nv2a PCRTC: read [0x%llx] -> %llx\n", addr, r);
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return r;
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}
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static void nv2a_pcrtc_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pcrtc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2AState *d = opaque;
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@ -302,7 +302,7 @@ static void nv2a_pcrtc_write(void *opaque, target_phys_addr_t addr,
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/* PRMCIO - aliases VGA CRTC and attribute controller registers */
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static uint64_t nv2a_prmcio_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2AState *d = opaque;
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uint64_t r = vga_ioport_read(&d->vga, addr);
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@ -310,7 +310,7 @@ static uint64_t nv2a_prmcio_read(void *opaque,
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NV2A_DPRINTF("nv2a PRMCIO: read [0x%llx] -> %llx\n", addr, r);
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return r;
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}
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static void nv2a_prmcio_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_prmcio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2AState *d = opaque;
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@ -337,12 +337,12 @@ static void nv2a_prmcio_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pramdac_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRAMDAC: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pramdac_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pramdac_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRAMDAC: [0x%llx] = 0x%02llx\n", addr, val);
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@ -350,12 +350,12 @@ static void nv2a_pramdac_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_prmdio_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMDIO: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_prmdio_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_prmdio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRMDIO: [0x%llx] = 0x%02llx\n", addr, val);
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@ -363,12 +363,12 @@ static void nv2a_prmdio_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_pramin_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRAMIN: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_pramin_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_pramin_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a PRAMIN: [0x%llx] = 0x%02llx\n", addr, val);
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@ -376,12 +376,12 @@ static void nv2a_pramin_write(void *opaque, target_phys_addr_t addr,
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static uint64_t nv2a_user_read(void *opaque,
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target_phys_addr_t addr, unsigned int size)
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hwaddr addr, unsigned int size)
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{
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NV2A_DPRINTF("nv2a USER: read [0x%llx]\n", addr);
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return 0;
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}
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static void nv2a_user_write(void *opaque, target_phys_addr_t addr,
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static void nv2a_user_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NV2A_DPRINTF("nv2a USER: [0x%llx] = 0x%02llx\n", addr, val);
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@ -392,7 +392,7 @@ static void nv2a_user_write(void *opaque, target_phys_addr_t addr,
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typedef struct NV2ABlockInfo {
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const char* name;
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target_phys_addr_t offset;
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hwaddr offset;
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uint64_t size;
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MemoryRegionOps ops;
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} NV2ABlockInfo;
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@ -48,7 +48,7 @@
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*/
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#define DEBUG
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//#define DEBUG
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#ifdef DEBUG
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# define XBOXPCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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@ -166,7 +166,7 @@ i2c_bus *mcpx_smbus_init(PCIBus *bus, qemu_irq *gsi)
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#define MCPX_SMBUS_BASE_BAR 1
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static void mcpx_smb_ioport_writeb(void *opaque, target_phys_addr_t addr,
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static void mcpx_smb_ioport_writeb(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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MCPX_SMBState *s = opaque;
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@ -175,7 +175,7 @@ static void mcpx_smb_ioport_writeb(void *opaque, target_phys_addr_t addr,
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amd756_smb_ioport_writeb(&s->smb, offset, val);
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}
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static uint64_t mcpx_smb_ioport_readb(void *opaque, target_phys_addr_t addr,
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static uint64_t mcpx_smb_ioport_readb(void *opaque, hwaddr addr,
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unsigned size)
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{
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MCPX_SMBState *s = opaque;
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