From 078189b327ae5c5727b51ec714d9663b1d0ca3df Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Thu, 21 Mar 2024 18:49:48 +0800 Subject: [PATCH] hw/intc: Update APLIC IDC after claiming iforce register Currently, QEMU only sets the iforce register to 0 and returns early when claiming the iforce register. However, this may leave mip.meip remains at 1 if a spurious external interrupt triggered by iforce register is the only pending interrupt to be claimed, and the interrupt cannot be lowered as expected. This commit fixes this issue by calling riscv_aplic_idc_update() to update the IDC status after the iforce register is claimed. Signed-off-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Message-ID: <20240321104951.12104-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 6a7fbfa861..fc5df0d598 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -488,6 +488,7 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc) if (!topi) { aplic->iforce[idc] = 0; + riscv_aplic_idc_update(aplic, idc); return 0; }