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hw/char/pl011: Replace magic values by register field definitions 

0x400 is Data Register Break Error (DR_BE),
0x10 is Line Control Register Fifo Enabled (LCR_FEN)
and 0x1 is Send Break (LCR_BRK).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230522153144.30610-7-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-05-22 10:37:30 +02:00
parent 22f7ff7f23
commit 0773885236
1 changed files with 15 additions and 7 deletions
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22
hw/char/pl011.c
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@ -54,6 +54,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
#define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10 #define PL011_FLAG_RXFE 0x10
/* Data Register, UARTDR */
#define DR_BE (1 << 10)
/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
#define INT_OE (1 << 10) #define INT_OE (1 << 10)
#define INT_BE (1 << 9) #define INT_BE (1 << 9)
@ -69,6 +72,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE)
#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS)
/* Line Control Register, UARTLCR_H */
#define LCR_FEN (1 << 4)
#define LCR_BRK (1 << 0)
static const unsigned char pl011_id_arm[8] = static const unsigned char pl011_id_arm[8] =
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
static const unsigned char pl011_id_luminary[8] = static const unsigned char pl011_id_luminary[8] =
@ -116,7 +123,7 @@ static void pl011_update(PL011State *s)
static bool pl011_is_fifo_enabled(PL011State *s) static bool pl011_is_fifo_enabled(PL011State *s)
{ {
return (s->lcr & 0x10) != 0; return (s->lcr & LCR_FEN) != 0;
} }
static inline unsigned pl011_get_fifo_depth(PL011State *s) static inline unsigned pl011_get_fifo_depth(PL011State *s)
@ -218,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s)
the threshold. However linux only reads the FIFO in response to an the threshold. However linux only reads the FIFO in response to an
interrupt. Triggering the interrupt when the FIFO is non-empty seems interrupt. Triggering the interrupt when the FIFO is non-empty seems
to make things work. */ to make things work. */
if (s->lcr & 0x10) if (s->lcr & LCR_FEN)
s->read_trigger = (s->ifl >> 1) & 0x1c; s->read_trigger = (s->ifl >> 1) & 0x1c;
else else
#endif #endif
@ -281,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset,
break; break;
case 11: /* UARTLCR_H */ case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */ /* Reset the FIFO state on FIFO enable or disable */
if ((s->lcr ^ value) & 0x10) { if ((s->lcr ^ value) & LCR_FEN) {
pl011_reset_fifo(s); pl011_reset_fifo(s);
} }
if ((s->lcr ^ value) & 0x1) { if ((s->lcr ^ value) & LCR_BRK) {
int break_enable = value & 0x1; int break_enable = value & LCR_BRK;
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable); &break_enable);
} }
@ -359,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size)
static void pl011_event(void *opaque, QEMUChrEvent event) static void pl011_event(void *opaque, QEMUChrEvent event)
{ {
if (event == CHR_EVENT_BREAK) if (event == CHR_EVENT_BREAK) {
pl011_put_fifo(opaque, 0x400); pl011_put_fifo(opaque, DR_BE);
}
} }
static void pl011_clock_update(void *opaque, ClockEvent event) static void pl011_clock_update(void *opaque, ClockEvent event)