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target/arm: Mark LDS{MIN,MAX} as signed operations
The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must be signed, so that the inputs are properly extended. Zero extend the result afterward, as needed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210602020720.47679-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3355,8 +3355,9 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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int o3_opc = extract32(insn, 12, 4);
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bool r = extract32(insn, 22, 1);
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bool a = extract32(insn, 23, 1);
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TCGv_i64 tcg_rs, clean_addr;
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TCGv_i64 tcg_rs, tcg_rt, clean_addr;
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AtomicThreeOpFn *fn = NULL;
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MemOp mop = s->be_data | size | MO_ALIGN;
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if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
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unallocated_encoding(s);
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@ -3377,9 +3378,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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break;
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case 004: /* LDSMAX */
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fn = tcg_gen_atomic_fetch_smax_i64;
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mop |= MO_SIGN;
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break;
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case 005: /* LDSMIN */
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fn = tcg_gen_atomic_fetch_smin_i64;
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mop |= MO_SIGN;
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break;
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case 006: /* LDUMAX */
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fn = tcg_gen_atomic_fetch_umax_i64;
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@ -3422,6 +3425,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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}
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tcg_rs = read_cpu_reg(s, rs, true);
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tcg_rt = cpu_reg(s, rt);
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if (o3_opc == 1) { /* LDCLR */
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tcg_gen_not_i64(tcg_rs, tcg_rs);
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@ -3430,8 +3434,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
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/* The tcg atomic primitives are all full barriers. Therefore we
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* can ignore the Acquire and Release bits of this instruction.
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*/
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fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
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s->be_data | size | MO_ALIGN);
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fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop);
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if ((mop & MO_SIGN) && size != MO_64) {
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tcg_gen_ext32u_i64(tcg_rt, tcg_rt);
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}
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}
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/*
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