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hw/intc: openpic: Clean up the styles 

Correct the multi-line comment format. No functional changes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Message-Id: <20210918032653.646370-3-bin.meng@windriver.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bin Meng 2021-09-18 11:26:53 +08:00 committed by David Gibson
parent 86229b68a2
commit 06caae8af0
2 changed files with 40 additions and 24 deletions
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53
hw/intc/openpic.c
View File

@ -47,7 +47,7 @@
#include "qemu/timer.h" #include "qemu/timer.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
//#define DEBUG_OPENPIC /* #define DEBUG_OPENPIC */
#ifdef DEBUG_OPENPIC #ifdef DEBUG_OPENPIC
static const int debug_openpic = 1; static const int debug_openpic = 1;
@ -118,7 +118,8 @@ static FslMpicInfo fsl_mpic_42 = {
#define ILR_INTTGT_CINT 0x01 /* critical */ #define ILR_INTTGT_CINT 0x01 /* critical */
#define ILR_INTTGT_MCP 0x02 /* machine check */ #define ILR_INTTGT_MCP 0x02 /* machine check */
/* The currently supported INTTGT values happen to be the same as QEMU's /*
* The currently supported INTTGT values happen to be the same as QEMU's
* openpic output codes, but don't depend on this. The output codes * openpic output codes, but don't depend on this. The output codes
* could change (unlikely, but...) or support could be added for * could change (unlikely, but...) or support could be added for
* more INTTGT values. * more INTTGT values.
@ -177,10 +178,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
uint32_t val, int idx); uint32_t val, int idx);
static void openpic_reset(DeviceState *d); static void openpic_reset(DeviceState *d);
/* Convert between openpic clock ticks and nanosecs. In the hardware the clock /*
frequency is driven by board inputs to the PIC which the PIC would then * Convert between openpic clock ticks and nanosecs. In the hardware the clock
divide by 4 or 8. For now hard code to 25MZ. * frequency is driven by board inputs to the PIC which the PIC would then
*/ * divide by 4 or 8. For now hard code to 25MZ.
*/
#define OPENPIC_TIMER_FREQ_MHZ 25 #define OPENPIC_TIMER_FREQ_MHZ 25
#define OPENPIC_TIMER_NS_PER_TICK (1000 / OPENPIC_TIMER_FREQ_MHZ) #define OPENPIC_TIMER_NS_PER_TICK (1000 / OPENPIC_TIMER_FREQ_MHZ)
static inline uint64_t ns_to_ticks(uint64_t ns) static inline uint64_t ns_to_ticks(uint64_t ns)
@ -253,7 +255,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
__func__, src->output, n_IRQ, active, was_active, __func__, src->output, n_IRQ, active, was_active,
dst->outputs_active[src->output]); dst->outputs_active[src->output]);
/* On Freescale MPIC, critical interrupts ignore priority, /*
* On Freescale MPIC, critical interrupts ignore priority,
* IACK, EOI, etc. Before MPIC v4.1 they also ignore * IACK, EOI, etc. Before MPIC v4.1 they also ignore
* masking. * masking.
*/ */
@ -276,7 +279,8 @@ static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
priority = IVPR_PRIORITY(src->ivpr); priority = IVPR_PRIORITY(src->ivpr);
/* Even if the interrupt doesn't have enough priority, /*
* Even if the interrupt doesn't have enough priority,
* it is still raised, in case ctpr is lowered later. * it is still raised, in case ctpr is lowered later.
*/ */
if (active) { if (active) {
@ -408,7 +412,8 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
} }
if (src->output != OPENPIC_OUTPUT_INT) { if (src->output != OPENPIC_OUTPUT_INT) {
/* Edge-triggered interrupts shouldn't be used /*
* Edge-triggered interrupts shouldn't be used
* with non-INT delivery, but just in case, * with non-INT delivery, but just in case,
* try to make it do something sane rather than * try to make it do something sane rather than
* cause an interrupt storm. This is close to * cause an interrupt storm. This is close to
@ -501,7 +506,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
{ {
uint32_t mask; uint32_t mask;
/* NOTE when implementing newer FSL MPIC models: starting with v4.0, /*
* NOTE when implementing newer FSL MPIC models: starting with v4.0,
* the polarity bit is read-only on internal interrupts. * the polarity bit is read-only on internal interrupts.
*/ */
mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
@ -511,7 +517,8 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
opp->src[n_IRQ].ivpr = opp->src[n_IRQ].ivpr =
(opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
/* For FSL internal interrupts, The sense bit is reserved and zero, /*
* For FSL internal interrupts, The sense bit is reserved and zero,
* and the interrupt is always level-triggered. Timers and IPIs * and the interrupt is always level-triggered. Timers and IPIs
* have no sense or polarity bits, and are edge-triggered. * have no sense or polarity bits, and are edge-triggered.
*/ */
@ -695,16 +702,20 @@ static void qemu_timer_cb(void *opaque)
openpic_set_irq(opp, n_IRQ, 0); openpic_set_irq(opp, n_IRQ, 0);
} }
/* If enabled is true, arranges for an interrupt to be raised val clocks into /*
the future, if enabled is false cancels the timer. */ * If enabled is true, arranges for an interrupt to be raised val clocks into
* the future, if enabled is false cancels the timer.
*/
static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled) static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
{ {
uint64_t ns = ticks_to_ns(val & ~TCCR_TOG); uint64_t ns = ticks_to_ns(val & ~TCCR_TOG);
/* A count of zero causes a timer to be set to expire immediately. This /*
effectively stops the simulation since the timer is constantly expiring * A count of zero causes a timer to be set to expire immediately. This
which prevents guest code execution, so we don't honor that * effectively stops the simulation since the timer is constantly expiring
configuration. On real hardware, this situation would generate an * which prevents guest code execution, so we don't honor that
interrupt on every clock cycle if the interrupt was unmasked. */ * configuration. On real hardware, this situation would generate an
* interrupt on every clock cycle if the interrupt was unmasked.
*/
if ((ns == 0) || !enabled) { if ((ns == 0) || !enabled) {
tmr->qemu_timer_active = false; tmr->qemu_timer_active = false;
tmr->tccr = tmr->tccr & TCCR_TOG; tmr->tccr = tmr->tccr & TCCR_TOG;
@ -717,8 +728,10 @@ static void openpic_tmr_set_tmr(OpenPICTimer *tmr, uint32_t val, bool enabled)
} }
} }
/* Returns the currrent tccr value, i.e., timer value (in clocks) with /*
appropriate TOG. */ * Returns the currrent tccr value, i.e., timer value (in clocks) with
* appropriate TOG.
*/
static uint64_t openpic_tmr_get_timer(OpenPICTimer *tmr) static uint64_t openpic_tmr_get_timer(OpenPICTimer *tmr)
{ {
uint64_t retval; uint64_t retval;

9
include/hw/ppc/openpic.h
View File

@ -51,7 +51,8 @@ typedef enum IRQType {
IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
} IRQType; } IRQType;
/* Round up to the nearest 64 IRQs so that the queue length /*
* Round up to the nearest 64 IRQs so that the queue length
* won't change when moving between 32 and 64 bit hosts. * won't change when moving between 32 and 64 bit hosts.
*/ */
#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
@ -101,8 +102,10 @@ typedef struct OpenPICTimer {
bool qemu_timer_active; /* Is the qemu_timer is running? */ bool qemu_timer_active; /* Is the qemu_timer is running? */
struct QEMUTimer *qemu_timer; struct QEMUTimer *qemu_timer;
struct OpenPICState *opp; /* Device timer is part of. */ struct OpenPICState *opp; /* Device timer is part of. */
/* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last /*
current_count written or read, only defined if qemu_timer_active. */ * The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
* current_count written or read, only defined if qemu_timer_active.
*/
uint64_t origin_time; uint64_t origin_time;
} OpenPICTimer; } OpenPICTimer;