mirror of https://github.com/xemu-project/xemu.git
Implement some more Gallileo registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2953 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths
parent
9566782b65
commit
05b4ff4357
353
hw/gt64xxx.c
353
hw/gt64xxx.c
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@ -23,9 +23,18 @@
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*/
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#include "vl.h"
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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//#define DEBUG
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#ifdef DEBUG
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#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define GT_REGS (0x1000 >> 2)
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/* CPU Configuration */
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@ -45,8 +54,6 @@ typedef target_phys_addr_t pci_addr_t;
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#define GT_PCI0IOHD (0x050 >> 2)
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#define GT_PCI0M0LD (0x058 >> 2)
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#define GT_PCI0M0HD (0x060 >> 2)
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#define GT_ISD (0x068 >> 2)
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#define GT_PCI0M1LD (0x080 >> 2)
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#define GT_PCI0M1HD (0x088 >> 2)
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#define GT_PCI1IOLD (0x090 >> 2)
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@ -55,8 +62,7 @@ typedef target_phys_addr_t pci_addr_t;
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#define GT_PCI1M0HD (0x0a8 >> 2)
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#define GT_PCI1M1LD (0x0b0 >> 2)
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#define GT_PCI1M1HD (0x0b8 >> 2)
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#define GT_PCI1M1LD (0x0b0 >> 2)
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#define GT_PCI1M1HD (0x0b8 >> 2)
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#define GT_ISD (0x068 >> 2)
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#define GT_SCS10AR (0x0d0 >> 2)
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#define GT_SCS32AR (0x0d8 >> 2)
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@ -330,6 +336,45 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
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/* Read-only registers, do nothing */
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break;
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/* SDRAM and Device Address Decode */
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case GT_SCS0LD:
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case GT_SCS0HD:
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case GT_SCS1LD:
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case GT_SCS1HD:
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case GT_SCS2LD:
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case GT_SCS2HD:
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case GT_SCS3LD:
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case GT_SCS3HD:
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case GT_CS0LD:
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case GT_CS0HD:
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case GT_CS1LD:
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case GT_CS1HD:
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case GT_CS2LD:
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case GT_CS2HD:
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case GT_CS3LD:
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case GT_CS3HD:
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case GT_BOOTLD:
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case GT_BOOTHD:
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case GT_ADERR:
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/* SDRAM Configuration */
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case GT_SDRAM_CFG:
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case GT_SDRAM_OPMODE:
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case GT_SDRAM_BM:
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case GT_SDRAM_ADDRDECODE:
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/* Accept and ignore SDRAM interleave configuration */
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s->regs[saddr] = val;
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break;
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/* Device Parameters */
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case GT_DEV_B0:
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case GT_DEV_B1:
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case GT_DEV_B2:
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case GT_DEV_B3:
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case GT_DEV_BOOT:
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/* Not implemented */
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dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
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break;
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/* ECC */
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case GT_ECC_ERRDATALO:
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case GT_ECC_ERRDATAHI:
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@ -339,16 +384,131 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
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/* Read-only registers, do nothing */
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break;
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/* DMA Record */
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case GT_DMA0_CNT:
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case GT_DMA1_CNT:
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case GT_DMA2_CNT:
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case GT_DMA3_CNT:
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case GT_DMA0_SA:
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case GT_DMA1_SA:
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case GT_DMA2_SA:
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case GT_DMA3_SA:
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case GT_DMA0_DA:
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case GT_DMA1_DA:
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case GT_DMA2_DA:
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case GT_DMA3_DA:
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case GT_DMA0_NEXT:
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case GT_DMA1_NEXT:
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case GT_DMA2_NEXT:
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case GT_DMA3_NEXT:
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case GT_DMA0_CUR:
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case GT_DMA1_CUR:
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case GT_DMA2_CUR:
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case GT_DMA3_CUR:
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/* Not implemented */
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dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
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break;
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/* DMA Channel Control */
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case GT_DMA0_CTRL:
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case GT_DMA1_CTRL:
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case GT_DMA2_CTRL:
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case GT_DMA3_CTRL:
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/* Not implemented */
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dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
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break;
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/* DMA Arbiter */
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case GT_DMA_ARB:
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/* Not implemented */
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dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
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break;
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/* Timer/Counter */
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case GT_TC0:
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case GT_TC1:
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case GT_TC2:
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case GT_TC3:
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case GT_TC_CONTROL:
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/* Not implemented */
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dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
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break;
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/* PCI Internal */
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case GT_PCI0_CMD:
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case GT_PCI1_CMD:
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s->regs[saddr] = val & 0x0401fc0f;
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break;
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case GT_PCI0_TOR:
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case GT_PCI0_BS_SCS10:
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case GT_PCI0_BS_SCS32:
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case GT_PCI0_BS_CS20:
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case GT_PCI0_BS_CS3BT:
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case GT_PCI1_IACK:
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case GT_PCI0_IACK:
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case GT_PCI0_BARE:
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case GT_PCI0_PREFMBR:
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case GT_PCI0_SCS10_BAR:
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case GT_PCI0_SCS32_BAR:
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case GT_PCI0_CS20_BAR:
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case GT_PCI0_CS3BT_BAR:
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case GT_PCI0_SSCS10_BAR:
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case GT_PCI0_SSCS32_BAR:
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case GT_PCI0_SCS3BT_BAR:
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case GT_PCI1_TOR:
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case GT_PCI1_BS_SCS10:
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case GT_PCI1_BS_SCS32:
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case GT_PCI1_BS_CS20:
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case GT_PCI1_BS_CS3BT:
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case GT_PCI1_BARE:
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case GT_PCI1_PREFMBR:
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case GT_PCI1_SCS10_BAR:
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case GT_PCI1_SCS32_BAR:
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case GT_PCI1_CS20_BAR:
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case GT_PCI1_CS3BT_BAR:
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case GT_PCI1_SSCS10_BAR:
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case GT_PCI1_SSCS32_BAR:
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case GT_PCI1_SCS3BT_BAR:
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case GT_PCI1_CFGADDR:
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case GT_PCI1_CFGDATA:
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/* not implemented */
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break;
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case GT_PCI0_CFGADDR:
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s->pci->config_reg = val & 0x80fffffc;
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break;
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case GT_PCI0_CFGDATA:
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pci_host_data_writel(s->pci, 0, val);
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if (s->pci->config_reg & (1u << 31))
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pci_host_data_writel(s->pci, 0, val);
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break;
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/* Interrupts */
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case GT_INTRCAUSE:
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/* not really implemented */
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s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
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s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
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dprintf("INTRCAUSE %x\n", val);
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break;
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case GT_INTRMASK:
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s->regs[saddr] = val & 0x3c3ffffe;
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dprintf("INTRMASK %x\n", val);
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break;
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case GT_PCI0_ICMASK:
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s->regs[saddr] = val & 0x03fffffe;
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dprintf("ICMASK %x\n", val);
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break;
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case GT_PCI0_SERR0MASK:
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s->regs[saddr] = val & 0x0000003f;
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dprintf("SERR0MASK %x\n", val);
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break;
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/* Reserved when only PCI_0 is configured. */
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case GT_HINTRCAUSE:
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case GT_CPU_INTSEL:
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case GT_PCI0_INTSEL:
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case GT_HINTRMASK:
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case GT_PCI0_HICMASK:
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case GT_PCI1_SERR1MASK:
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/* not implemented */
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break;
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/* SDRAM Parameters */
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@ -362,9 +522,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
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break;
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default:
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#if 0
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printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
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#endif
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dprintf ("Bad register offset 0x%x\n", (int)addr);
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break;
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}
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}
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@ -420,6 +578,18 @@ static uint32_t gt64120_readl (void *opaque,
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break;
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case GT_CPU:
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case GT_SCS10LD:
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case GT_SCS10HD:
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case GT_SCS32LD:
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case GT_SCS32HD:
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case GT_CS20LD:
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case GT_CS20HD:
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case GT_CS3BOOTLD:
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case GT_CS3BOOTHD:
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case GT_SCS10AR:
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case GT_SCS32AR:
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case GT_CS20R:
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case GT_CS3BOOTR:
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case GT_PCI0IOLD:
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case GT_PCI0M0LD:
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case GT_PCI0M1LD:
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@ -432,14 +602,13 @@ static uint32_t gt64120_readl (void *opaque,
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case GT_PCI1IOHD:
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case GT_PCI1M0HD:
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case GT_PCI1M1HD:
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case GT_PCI0_CMD:
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case GT_PCI1_CMD:
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case GT_PCI0IOREMAP:
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case GT_PCI0M0REMAP:
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case GT_PCI0M1REMAP:
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case GT_PCI1IOREMAP:
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case GT_PCI1M0REMAP:
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case GT_PCI1M1REMAP:
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case GT_ISD:
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val = s->regs[saddr];
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break;
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case GT_PCI0_IACK:
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@ -447,6 +616,37 @@ static uint32_t gt64120_readl (void *opaque,
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val = pic_read_irq(isa_pic);
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break;
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/* SDRAM and Device Address Decode */
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case GT_SCS0LD:
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case GT_SCS0HD:
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case GT_SCS1LD:
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case GT_SCS1HD:
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case GT_SCS2LD:
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case GT_SCS2HD:
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case GT_SCS3LD:
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case GT_SCS3HD:
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case GT_CS0LD:
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case GT_CS0HD:
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case GT_CS1LD:
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case GT_CS1HD:
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case GT_CS2LD:
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case GT_CS2HD:
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case GT_CS3LD:
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case GT_CS3HD:
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case GT_BOOTLD:
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case GT_BOOTHD:
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case GT_ADERR:
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val = s->regs[saddr];
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break;
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/* SDRAM Configuration */
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case GT_SDRAM_CFG:
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case GT_SDRAM_OPMODE:
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case GT_SDRAM_BM:
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case GT_SDRAM_ADDRDECODE:
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val = s->regs[saddr];
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break;
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/* SDRAM Parameters */
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case GT_SDRAM_B0:
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case GT_SDRAM_B1:
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@ -457,27 +657,146 @@ static uint32_t gt64120_readl (void *opaque,
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val = s->regs[saddr];
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break;
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/* Device Parameters */
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case GT_DEV_B0:
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case GT_DEV_B1:
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case GT_DEV_B2:
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case GT_DEV_B3:
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case GT_DEV_BOOT:
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val = s->regs[saddr];
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break;
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/* DMA Record */
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case GT_DMA0_CNT:
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case GT_DMA1_CNT:
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case GT_DMA2_CNT:
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case GT_DMA3_CNT:
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case GT_DMA0_SA:
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case GT_DMA1_SA:
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case GT_DMA2_SA:
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case GT_DMA3_SA:
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case GT_DMA0_DA:
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case GT_DMA1_DA:
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case GT_DMA2_DA:
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case GT_DMA3_DA:
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case GT_DMA0_NEXT:
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case GT_DMA1_NEXT:
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case GT_DMA2_NEXT:
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case GT_DMA3_NEXT:
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case GT_DMA0_CUR:
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case GT_DMA1_CUR:
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case GT_DMA2_CUR:
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case GT_DMA3_CUR:
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val = s->regs[saddr];
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break;
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/* DMA Channel Control */
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case GT_DMA0_CTRL:
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case GT_DMA1_CTRL:
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case GT_DMA2_CTRL:
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case GT_DMA3_CTRL:
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val = s->regs[saddr];
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break;
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/* DMA Arbiter */
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case GT_DMA_ARB:
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val = s->regs[saddr];
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break;
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/* Timer/Counter */
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case GT_TC0:
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case GT_TC1:
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case GT_TC2:
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case GT_TC3:
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case GT_TC_CONTROL:
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val = s->regs[saddr];
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break;
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/* PCI Internal */
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case GT_PCI0_CFGADDR:
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val = s->pci->config_reg;
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break;
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case GT_PCI0_CFGDATA:
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val = pci_host_data_readl(s->pci, 0);
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if (!(s->pci->config_reg & (1u << 31)))
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val = 0xffffffff;
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else
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val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
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break;
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case GT_PCI0_CMD:
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case GT_PCI0_TOR:
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case GT_PCI0_BS_SCS10:
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case GT_PCI0_BS_SCS32:
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case GT_PCI0_BS_CS20:
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case GT_PCI0_BS_CS3BT:
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case GT_PCI1_IACK:
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case GT_PCI0_BARE:
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case GT_PCI0_PREFMBR:
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case GT_PCI0_SCS10_BAR:
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case GT_PCI0_SCS32_BAR:
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case GT_PCI0_CS20_BAR:
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case GT_PCI0_CS3BT_BAR:
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case GT_PCI0_SSCS10_BAR:
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case GT_PCI0_SSCS32_BAR:
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case GT_PCI0_SCS3BT_BAR:
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case GT_PCI1_CMD:
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case GT_PCI1_TOR:
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case GT_PCI1_BS_SCS10:
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case GT_PCI1_BS_SCS32:
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case GT_PCI1_BS_CS20:
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case GT_PCI1_BS_CS3BT:
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case GT_PCI1_BARE:
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case GT_PCI1_PREFMBR:
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case GT_PCI1_SCS10_BAR:
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case GT_PCI1_SCS32_BAR:
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case GT_PCI1_CS20_BAR:
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case GT_PCI1_CS3BT_BAR:
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case GT_PCI1_SSCS10_BAR:
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case GT_PCI1_SSCS32_BAR:
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case GT_PCI1_SCS3BT_BAR:
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case GT_PCI1_CFGADDR:
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case GT_PCI1_CFGDATA:
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val = s->regs[saddr];
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break;
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/* Interrupts */
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case GT_INTRCAUSE:
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val = s->regs[saddr];
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dprintf("INTRCAUSE %x\n", val);
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break;
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case GT_INTRMASK:
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val = s->regs[saddr];
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dprintf("INTRMASK %x\n", val);
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break;
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case GT_PCI0_ICMASK:
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val = s->regs[saddr];
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dprintf("ICMASK %x\n", val);
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break;
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case GT_PCI0_SERR0MASK:
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val = s->regs[saddr];
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dprintf("SERR0MASK %x\n", val);
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break;
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/* Reserved when only PCI_0 is configured. */
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case GT_HINTRCAUSE:
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case GT_CPU_INTSEL:
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case GT_PCI0_INTSEL:
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case GT_HINTRMASK:
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case GT_PCI0_HICMASK:
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case GT_PCI1_SERR1MASK:
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val = s->regs[saddr];
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break;
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default:
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val = s->regs[saddr];
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#if 0
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printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
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#endif
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dprintf ("Bad register offset 0x%x\n", (int)addr);
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break;
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap32(val);
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#else
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return val;
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *gt64120_write[] = {
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