ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ARM: Fix decoding of VFP forms of VCVT between float and int/fixed 

Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
This commit is contained in:
Peter Maydell 2010-12-07 15:37:34 +00:00
parent 2c9adbda72
commit 04595bf66f
1 changed files with 12 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
target-arm/translate.c
View File

@ -2870,16 +2870,18 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
VFP_DREG_N(rn, insn); VFP_DREG_N(rn, insn);
} }
if (op == 15 && (rn == 15 || rn > 17)) { if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
/* Integer or single precision destination. */ /* Integer or single precision destination. */
rd = VFP_SREG_D(insn); rd = VFP_SREG_D(insn);
} else { } else {
VFP_DREG_D(rd, insn); VFP_DREG_D(rd, insn);
} }
if (op == 15 &&
if (op == 15 && (rn == 16 || rn == 17)) { (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
/* Integer source. */ /* VCVT from int is always from S reg regardless of dp bit.
rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1); * VCVT with immediate frac_bits has same format as SREG_M
*/
rm = VFP_SREG_M(insn);
} else { } else {
VFP_DREG_M(rm, insn); VFP_DREG_M(rm, insn);
} }
@ -2891,6 +2893,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else { } else {
rd = VFP_SREG_D(insn); rd = VFP_SREG_D(insn);
} }
/* NB that we implicitly rely on the encoding for the frac_bits
* in VCVT of fixed to float being the same as that of an SREG_M
*/
rm = VFP_SREG_M(insn); rm = VFP_SREG_M(insn);
} }
@ -3179,8 +3184,8 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
/* Write back the result. */ /* Write back the result. */
if (op == 15 && (rn >= 8 && rn <= 11)) if (op == 15 && (rn >= 8 && rn <= 11))
; /* Comparison, do nothing. */ ; /* Comparison, do nothing. */
else if (op == 15 && rn > 17) else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
/* Integer result. */ /* VCVT double to int: always integer result. */
gen_mov_vreg_F0(0, rd); gen_mov_vreg_F0(0, rd);
else if (op == 15 && rn == 15) else if (op == 15 && rn == 15)
/* conversion */ /* conversion */