From 03bc4f66280023cba17f8cdbd3a5b6589db343be Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Sat, 21 Dec 2013 03:02:50 +0100 Subject: [PATCH] piix: fix 32bit pci hole Make the 32bit pci hole start at end of ram, so all possible address space is covered. We used to try and make addresses aligned so they are easier to cover with MTRRs, but since they are cosmetic on KVM, this is probably not worth worrying about. Of course the firmware can use less than that. Leaving space unused is no problem, mapping pci bars outside the hole causes problems though. Signed-off-by: Gerd Hoffmann Signed-off-by: Laszlo Ersek Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin (cherry picked from commit ddaaefb4dd427d6d2e41c1cfbe0cd8d8e8d6aad9) Signed-off-by: Michael Roth --- hw/i386/pc_piix.c | 1 + hw/pci-host/piix.c | 11 ++--------- include/hw/i386/pc.h | 1 + 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 29b47d4d99..cc9b273bc5 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -149,6 +149,7 @@ static void pc_init1(QEMUMachineInitArgs *args, if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi, system_memory, system_io, args->ram_size, + below_4g_mem_size, above_4g_mem_size, pci_memory, ram_memory); } else { diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 63be7f6cee..4229d09acf 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -311,6 +311,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, + ram_addr_t below_4g_mem_size, ram_addr_t above_4g_mem_size, MemoryRegion *pci_address_space, MemoryRegion *ram_memory) @@ -340,15 +341,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, f->ram_memory = ram_memory; i440fx = I440FX_PCI_HOST_BRIDGE(dev); - /* Set PCI window size the way seabios has always done it. */ - /* Power of 2 so bios can cover it with a single MTRR */ - if (ram_size <= 0x80000000) { - i440fx->pci_info.w32.begin = 0x80000000; - } else if (ram_size <= 0xc0000000) { - i440fx->pci_info.w32.begin = 0xc0000000; - } else { - i440fx->pci_info.w32.begin = 0xe0000000; - } + i440fx->pci_info.w32.begin = below_4g_mem_size; /* setup pci memory mapping */ pc_pci_as_mapping_init(OBJECT(f), f->system_memory, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 8ea1a98728..2a4a0947e6 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -179,6 +179,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, + ram_addr_t below_4g_mem_size, ram_addr_t above_4g_mem_size, MemoryRegion *pci_memory, MemoryRegion *ram_memory);