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target/arm: Reorg do_coproc_insn 

Move the ri == NULL case to the top of the function and return.
This allows the else to be removed and the code unindented.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230106194451.1213153-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-01-06 11:44:50 -08:00 committed by Peter Maydell
parent b3aa2f2128
commit 0371fa90a1
1 changed files with 203 additions and 203 deletions
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60
target/arm/translate.c
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@ -4715,11 +4715,32 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
bool isread, int rt, int rt2)
{
const ARMCPRegInfo *ri;
bool need_exit_tb;
ri = get_arm_cp_reginfo(s->cp_regs,
ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
if (ri) {
bool need_exit_tb;
if (!ri) {
/*
* Unknown register; this might be a guest error or a QEMU
* unimplemented feature.
*/
if (is64) {
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
"64 bit system register cp:%d opc1: %d crm:%d "
"(%s)\n",
isread ? "read" : "write", cpnum, opc1, crm,
s->ns ? "non-secure" : "secure");
} else {
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
"system register cp:%d opc1:%d crn:%d crm:%d "
"opc2:%d (%s)\n",
isread ? "read" : "write", cpnum, opc1, crn,
crm, opc2, s->ns ? "non-secure" : "secure");
}
unallocated_encoding(s);
return;
}
/* Check access permissions */
if (!cp_access_ok(s->current_el, ri, isread)) {
@ -4729,14 +4750,16 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
if (s->hstr_active || ri->accessfn ||
(arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
/* Emit code to perform further access permissions checks at
/*
* Emit code to perform further access permissions checks at
* runtime; this may result in an exception.
* Note that on XScale all cp0..c13 registers do an access check
* call in order to handle c15_cpar.
*/
uint32_t syndrome;
/* Note that since we are an implementation which takes an
/*
* Note that since we are an implementation which takes an
* exception on a trapped conditional instruction only if the
* instruction passes its condition code check, we can take
* advantage of the clause in the ARM ARM that allows us to set
@ -4764,7 +4787,8 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
}
break;
default:
/* ARMv8 defines that only coprocessors 14 and 15 exist,
/*
* ARMv8 defines that only coprocessors 14 and 15 exist,
* so this can only happen if this is an ARMv7 or earlier CPU,
* in which case the syndrome information won't actually be
* guest visible.
@ -4869,8 +4893,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
tcg_temp_free_i32(tmplo);
tcg_temp_free_i32(tmphi);
if (ri->writefn) {
gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri),
tmp64);
gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tmp64);
} else {
tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
}
@ -4906,29 +4929,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
if (need_exit_tb) {
gen_lookup_tb(s);
}
return;
}
/* Unknown register; this might be a guest error or a QEMU
* unimplemented feature.
*/
if (is64) {
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
"64 bit system register cp:%d opc1: %d crm:%d "
"(%s)\n",
isread ? "read" : "write", cpnum, opc1, crm,
s->ns ? "non-secure" : "secure");
} else {
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
"system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
"(%s)\n",
isread ? "read" : "write", cpnum, opc1, crn, crm, opc2,
s->ns ? "non-secure" : "secure");
}
unallocated_encoding(s);
return;
}
/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */