mirror of https://github.com/xemu-project/xemu.git
target/riscv: Improve delivery of guest external interrupts
The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish response to serial console input and other I/O events. To solve this, we check and inject interrupt after setting V=1. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-5-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -326,6 +326,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
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}
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}
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env->virt = set_field(env->virt, VIRT_ONOFF, enable);
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env->virt = set_field(env->virt, VIRT_ONOFF, enable);
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if (enable) {
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/*
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* The guest external interrupts from an interrupt controller are
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* delivered only when the Guest/VM is running (i.e. V=1). This means
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* any guest external interrupt which is triggered while the Guest/VM
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* is not running (i.e. V=0) will be missed on QEMU resulting in guest
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* with sluggish response to serial console input and other I/O events.
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*
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* To solve this, we check and inject interrupt after setting V=1.
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*/
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riscv_cpu_update_mip(env_archcpu(env), 0, 0);
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}
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}
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}
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bool riscv_cpu_two_stage_lookup(int mmu_idx)
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bool riscv_cpu_two_stage_lookup(int mmu_idx)
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