mirror of https://github.com/xemu-project/xemu.git
Accelerators patches
- MAINTAINERS: Update Roman Bolshakov email address - HAX: Fix a memory leak - HAX/NVMM/WHPX/HVF: Rename per-accel state as AccelCPUState - KVM: Restrict specific fields from ArchCPU - WHPX: Re-enable cross-build gitlab-ci job on case sensitive filesystems - WHPX: Fix error message when setting ProcessorCount fails - exec/memory: Add definitions for memory listener priorities -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmScVtkACgkQ4+MsLN6t wN7p8A//RXuX9gLFT35zx+5axocU3/XBbCsQWSvzzkYoXxmC/TLxvivO66NPGMc0 C76b1FJUoLS/u9SyJUeIeYkL0rjkzARUKcRpiJXM21WM6ou8Nkz0kuI4ouowt+4K i/4chTjxlN5/4PKlHHcX9ZUJ9acVj01zO1BCuj/bVsxO6WMT1kjL+kplVxxFR3aW tlbYtUT3v4xmp94FfE2Q9lR25z4usrGnmz2rchaadlVc43kmsNcQRx+EoUdi148n lkViRR90sacYPX586s2yxhPpUdtrXjJmEdX0X00urdPqljkRxekHtyTqG4CRZi+K hG5NztK7p37GNNXZroL0gpHyr9IX6hZ3o8rmN3IiCOGU6BgQBRUhvvG2sblwcJ1A SSiBK4RWtgyIGWt4U6PgVj8IAu55JuqT5xR2r34fH/zccxXlp/B13vadGs7TUK15 oHDUT4GnKL2R29lVFTl95BzsxwaMtbB9w01CLJk8va2T/97eqtFgvJyuVC9vZb0N 41u2RkinaQZ+hbq9TP1G21zpG0eyucEMIQ6loUd7+G3KJFjFfB4JzE2VDm0Y/OVy 77cEEQ67wts29fMNSqqPIQCMttDrNj7JqMMknGBQS2iHPgF+B3KjwIjnRaMBt73I CKPITOJPmb+kvIUsK3KlONdicEG57cBxFBTZW5+P9pJXF5izrAY= =b9hj -----END PGP SIGNATURE----- Merge tag 'accel-20230628' of https://github.com/philmd/qemu into staging Accelerators patches - MAINTAINERS: Update Roman Bolshakov email address - HAX: Fix a memory leak - HAX/NVMM/WHPX/HVF: Rename per-accel state as AccelCPUState - KVM: Restrict specific fields from ArchCPU - WHPX: Re-enable cross-build gitlab-ci job on case sensitive filesystems - WHPX: Fix error message when setting ProcessorCount fails - exec/memory: Add definitions for memory listener priorities # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmScVtkACgkQ4+MsLN6t # wN7p8A//RXuX9gLFT35zx+5axocU3/XBbCsQWSvzzkYoXxmC/TLxvivO66NPGMc0 # C76b1FJUoLS/u9SyJUeIeYkL0rjkzARUKcRpiJXM21WM6ou8Nkz0kuI4ouowt+4K # i/4chTjxlN5/4PKlHHcX9ZUJ9acVj01zO1BCuj/bVsxO6WMT1kjL+kplVxxFR3aW # tlbYtUT3v4xmp94FfE2Q9lR25z4usrGnmz2rchaadlVc43kmsNcQRx+EoUdi148n # lkViRR90sacYPX586s2yxhPpUdtrXjJmEdX0X00urdPqljkRxekHtyTqG4CRZi+K # hG5NztK7p37GNNXZroL0gpHyr9IX6hZ3o8rmN3IiCOGU6BgQBRUhvvG2sblwcJ1A # SSiBK4RWtgyIGWt4U6PgVj8IAu55JuqT5xR2r34fH/zccxXlp/B13vadGs7TUK15 # oHDUT4GnKL2R29lVFTl95BzsxwaMtbB9w01CLJk8va2T/97eqtFgvJyuVC9vZb0N # 41u2RkinaQZ+hbq9TP1G21zpG0eyucEMIQ6loUd7+G3KJFjFfB4JzE2VDm0Y/OVy # 77cEEQ67wts29fMNSqqPIQCMttDrNj7JqMMknGBQS2iHPgF+B3KjwIjnRaMBt73I # CKPITOJPmb+kvIUsK3KlONdicEG57cBxFBTZW5+P9pJXF5izrAY= # =b9hj # -----END PGP SIGNATURE----- # gpg: Signature made Wed 28 Jun 2023 05:50:49 PM CEST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'accel-20230628' of https://github.com/philmd/qemu: (30 commits) exec/memory: Add symbol for the min value of memory listener priority exec/memory: Add symbol for memory listener priority for device backend exec/memory: Add symbolic value for memory listener priority for accel target/i386/WHPX: Fix error message when fail to set ProcessorCount target/riscv: Restrict KVM-specific fields from ArchCPU target/ppc: Restrict KVM-specific fields from ArchCPU target/arm: Restrict KVM-specific fields from ArchCPU hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' header hw/intc/arm_gic: Rename 'first_cpu' argument hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers accel/kvm: Declare kvm_direct_msi_allowed in stubs accel/kvm: Re-include "exec/memattrs.h" header accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUState accel: Rename 'cpu_state' -> 'cs' accel: Inline WHPX get_whpx_vcpu() accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUState accel: Remove WHPX unreachable error path accel: Inline NVMM get_qemu_vcpu() accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState accel: Remove NVMM unreachable error path ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
commit
017b2e7363
3
.mailmap
3
.mailmap
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@ -76,9 +76,10 @@ Paul Burton <paulburton@kernel.org> <pburton@wavecomp.com>
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Philippe Mathieu-Daudé <philmd@linaro.org> <f4bug@amsat.org>
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Philippe Mathieu-Daudé <philmd@linaro.org> <philmd@redhat.com>
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Philippe Mathieu-Daudé <philmd@linaro.org> <philmd@fungible.com>
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Roman Bolshakov <rbolshakov@ddn.com> <r.bolshakov@yadro.com>
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Stefan Brankovic <stefan.brankovic@syrmia.com> <stefan.brankovic@rt-rk.com.com>
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Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
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Taylor Simpson <ltaylorsimpson@gmail.com> <tsimpson@quicinc.com>
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Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
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# Also list preferred name forms where people have changed their
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# git author config, or had utf8/latin1 encoding issues.
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@ -498,14 +498,14 @@ F: target/arm/hvf/
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X86 HVF CPUs
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M: Cameron Esfahani <dirty@apple.com>
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M: Roman Bolshakov <r.bolshakov@yadro.com>
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M: Roman Bolshakov <rbolshakov@ddn.com>
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W: https://wiki.qemu.org/Features/HVF
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S: Maintained
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F: target/i386/hvf/
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HVF
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M: Cameron Esfahani <dirty@apple.com>
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M: Roman Bolshakov <r.bolshakov@yadro.com>
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M: Roman Bolshakov <rbolshakov@ddn.com>
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W: https://wiki.qemu.org/Features/HVF
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S: Maintained
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F: accel/hvf/
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@ -304,7 +304,7 @@ static void hvf_region_del(MemoryListener *listener,
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static MemoryListener hvf_memory_listener = {
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.name = "hvf",
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.priority = 10,
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.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
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.region_add = hvf_region_add,
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.region_del = hvf_region_del,
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.log_start = hvf_log_start,
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@ -372,19 +372,19 @@ type_init(hvf_type_init);
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static void hvf_vcpu_destroy(CPUState *cpu)
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{
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hv_return_t ret = hv_vcpu_destroy(cpu->hvf->fd);
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hv_return_t ret = hv_vcpu_destroy(cpu->accel->fd);
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assert_hvf_ok(ret);
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hvf_arch_vcpu_destroy(cpu);
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g_free(cpu->hvf);
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cpu->hvf = NULL;
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g_free(cpu->accel);
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cpu->accel = NULL;
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}
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static int hvf_init_vcpu(CPUState *cpu)
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{
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int r;
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cpu->hvf = g_malloc0(sizeof(*cpu->hvf));
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cpu->accel = g_new0(AccelCPUState, 1);
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/* init cpu signals */
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struct sigaction sigact;
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@ -393,18 +393,19 @@ static int hvf_init_vcpu(CPUState *cpu)
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sigact.sa_handler = dummy_signal;
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sigaction(SIG_IPI, &sigact, NULL);
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pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask);
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sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI);
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pthread_sigmask(SIG_BLOCK, NULL, &cpu->accel->unblock_ipi_mask);
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sigdelset(&cpu->accel->unblock_ipi_mask, SIG_IPI);
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#ifdef __aarch64__
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r = hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit, NULL);
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r = hv_vcpu_create(&cpu->accel->fd,
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(hv_vcpu_exit_t **)&cpu->accel->exit, NULL);
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#else
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r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);
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r = hv_vcpu_create((hv_vcpuid_t *)&cpu->accel->fd, HV_VCPU_DEFAULT);
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#endif
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cpu->vcpu_dirty = 1;
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assert_hvf_ok(r);
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cpu->hvf->guest_debug_enabled = false;
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cpu->accel->guest_debug_enabled = false;
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return hvf_arch_init_vcpu(cpu);
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}
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@ -1105,6 +1105,7 @@ static MemoryListener kvm_coalesced_pio_listener = {
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.name = "kvm-coalesced-pio",
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.coalesced_io_add = kvm_coalesce_pio_add,
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.coalesced_io_del = kvm_coalesce_pio_del,
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.priority = MEMORY_LISTENER_PRIORITY_MIN,
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};
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int kvm_check_extension(KVMState *s, unsigned int extension)
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@ -1777,7 +1778,7 @@ void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml,
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kml->listener.commit = kvm_region_commit;
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kml->listener.log_start = kvm_log_start;
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kml->listener.log_stop = kvm_log_stop;
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kml->listener.priority = 10;
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kml->listener.priority = MEMORY_LISTENER_PRIORITY_ACCEL;
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kml->listener.name = name;
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if (s->kvm_dirty_ring_size) {
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@ -1802,7 +1803,7 @@ static MemoryListener kvm_io_listener = {
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.name = "kvm-io",
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.eventfd_add = kvm_io_ioeventfd_add,
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.eventfd_del = kvm_io_ioeventfd_del,
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.priority = 10,
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.priority = MEMORY_LISTENER_PRIORITY_DEV_BACKEND,
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};
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int kvm_set_irq(KVMState *s, int irq, int level)
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@ -27,6 +27,7 @@ bool kvm_allowed;
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bool kvm_readonly_mem_allowed;
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bool kvm_ioeventfd_any_length_allowed;
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bool kvm_msi_use_devid;
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bool kvm_direct_msi_allowed;
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void kvm_flush_coalesced_mmio_buffer(void)
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{
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@ -152,8 +152,4 @@ void mttcg_start_vcpu_thread(CPUState *cpu)
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qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn,
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cpu, QEMU_THREAD_JOINABLE);
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#ifdef _WIN32
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cpu->hThread = qemu_thread_get_handle(cpu->thread);
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#endif
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}
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@ -329,9 +329,6 @@ void rr_start_vcpu_thread(CPUState *cpu)
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single_tcg_halt_cond = cpu->halt_cond;
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single_tcg_cpu_thread = cpu->thread;
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#ifdef _WIN32
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cpu->hThread = qemu_thread_get_handle(cpu->thread);
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#endif
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} else {
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/* we share the thread */
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cpu->thread = single_tcg_cpu_thread;
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|
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|
@ -558,7 +558,7 @@ When CI tasks, maintainers or yourself report a Docker test failure, follow the
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below steps to debug it:
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1. Locally reproduce the failure with the reported command line. E.g. run
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``make docker-test-mingw@fedora J=8``.
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``make docker-test-mingw@fedora-win64-cross J=8``.
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2. Add "V=1" to the command line, try again, to see the verbose output.
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3. Further add "DEBUG=1" to the command line. This will pause in a shell prompt
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in the container right before testing starts. You could either manually
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@ -23,6 +23,7 @@
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/kvm.h"
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#include "sysemu/numa.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
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@ -36,6 +37,7 @@
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#include "hw/ide/internal.h"
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#include "hw/ide/ahci_internal.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "hw/loader.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/qdev-properties.h"
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@ -48,12 +48,12 @@
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/arm/virt.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "hw/mem/nvdimm.h"
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#include "hw/platform-bus.h"
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#include "sysemu/numa.h"
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#include "sysemu/reset.h"
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#include "sysemu/tpm.h"
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#include "kvm_arm.h"
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#include "migration/vmstate.h"
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#include "hw/acpi/ghes.h"
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#include "hw/acpi/viot.h"
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@ -63,6 +63,7 @@
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#include "hw/arm/fdt.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "hw/irq.h"
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#include "kvm_arm.h"
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#include "hw/firmware/smbios.h"
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|
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|
@ -45,7 +45,7 @@ static MemoryListener xen_memory_listener = {
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.log_sync = NULL,
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.log_global_start = NULL,
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.log_global_stop = NULL,
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.priority = 10,
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.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
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};
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struct XenArmState {
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|
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@ -467,7 +467,7 @@ static MemoryListener xen_memory_listener = {
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.log_sync = xen_log_sync,
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.log_global_start = xen_log_global_start,
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.log_global_stop = xen_log_global_stop,
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.priority = 10,
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.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
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};
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static void regs_to_cpu(vmware_regs_t *vmport_regs, ioreq_t *req)
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|
|
|
@ -21,10 +21,12 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "gic_internal.h"
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#include "hw/arm/linux-boot-if.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "sysemu/kvm.h"
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static int gic_pre_save(void *opaque)
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{
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|
@ -233,12 +235,12 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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|||
}
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}
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static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
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static inline void arm_gic_common_reset_irq_state(GICState *s, int cidx,
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int resetprio)
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{
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int i, j;
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||||
|
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for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
|
||||
for (i = cidx; i < cidx + s->num_cpu; i++) {
|
||||
if (s->revision == REV_11MPCORE) {
|
||||
s->priority_mask[i] = 0xf0;
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||||
} else {
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|
@ -393,3 +395,8 @@ static void register_types(void)
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|||
}
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||||
type_init(register_types)
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|
||||
const char *gic_class_name(void)
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{
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return kvm_irqchip_in_kernel() ? "kvm-arm-gic" : "arm_gic";
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||||
}
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||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include "qemu/osdep.h"
|
||||
#include "qapi/error.h"
|
||||
#include "qemu/module.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "hw/core/cpu.h"
|
||||
#include "hw/intc/arm_gicv3_common.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
|
@ -608,3 +609,16 @@ static void register_types(void)
|
|||
}
|
||||
|
||||
type_init(register_types)
|
||||
|
||||
const char *gicv3_class_name(void)
|
||||
{
|
||||
if (kvm_irqchip_in_kernel()) {
|
||||
return "kvm-arm-gicv3";
|
||||
} else {
|
||||
if (kvm_enabled()) {
|
||||
error_report("Userspace GICv3 is not supported with KVM");
|
||||
exit(1);
|
||||
}
|
||||
return "arm-gicv3";
|
||||
}
|
||||
}
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include "hw/intc/arm_gicv3_its_common.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
#include "sysemu/kvm.h"
|
||||
|
||||
static int gicv3_its_pre_save(void *opaque)
|
||||
{
|
||||
|
@ -158,3 +159,14 @@ static void gicv3_its_common_register_types(void)
|
|||
}
|
||||
|
||||
type_init(gicv3_its_common_register_types)
|
||||
|
||||
const char *its_class_name(void)
|
||||
{
|
||||
if (kvm_irqchip_in_kernel()) {
|
||||
/* KVM implementation requires this capability */
|
||||
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
|
||||
} else {
|
||||
/* Software emulation based model */
|
||||
return "arm-gicv3-its";
|
||||
}
|
||||
}
|
||||
|
|
|
@ -765,7 +765,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env)
|
|||
tlb->mas7_3 = 0;
|
||||
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
env->tlb_dirty = true;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ppce500_cpu_reset_sec(void *opaque)
|
||||
|
|
|
@ -83,7 +83,9 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
|
|||
tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
|
||||
tlb->mas7_3 = pa & TARGET_PAGE_MASK;
|
||||
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
|
||||
#ifdef CONFIG_KVM
|
||||
env->tlb_dirty = true;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void spin_kick(CPUState *cs, run_on_cpu_data data)
|
||||
|
|
|
@ -217,7 +217,7 @@ void proxy_memory_listener_configure(ProxyMemoryListener *proxy_listener,
|
|||
proxy_listener->listener.commit = proxy_memory_listener_commit;
|
||||
proxy_listener->listener.region_add = proxy_memory_listener_region_addnop;
|
||||
proxy_listener->listener.region_nop = proxy_memory_listener_region_addnop;
|
||||
proxy_listener->listener.priority = 10;
|
||||
proxy_listener->listener.priority = MEMORY_LISTENER_PRIORITY_DEV_BACKEND;
|
||||
proxy_listener->listener.name = "proxy";
|
||||
|
||||
memory_listener_register(&proxy_listener->listener,
|
||||
|
|
|
@ -1444,7 +1444,7 @@ int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
|
|||
.log_sync = vhost_log_sync,
|
||||
.log_global_start = vhost_log_global_start,
|
||||
.log_global_stop = vhost_log_global_stop,
|
||||
.priority = 10
|
||||
.priority = MEMORY_LISTENER_PRIORITY_DEV_BACKEND
|
||||
};
|
||||
|
||||
hdev->iommu_listener = (MemoryListener) {
|
||||
|
|
|
@ -155,7 +155,7 @@ MemoryListener xen_io_listener = {
|
|||
.name = "xen-io",
|
||||
.region_add = xen_io_add,
|
||||
.region_del = xen_io_del,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
DeviceListener xen_device_listener = {
|
||||
|
|
|
@ -691,14 +691,14 @@ static const MemoryListener xen_pt_memory_listener = {
|
|||
.name = "xen-pt-mem",
|
||||
.region_add = xen_pt_region_add,
|
||||
.region_del = xen_pt_region_del,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
static const MemoryListener xen_pt_io_listener = {
|
||||
.name = "xen-pt-io",
|
||||
.region_add = xen_pt_io_region_add,
|
||||
.region_del = xen_pt_io_region_del,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
/* destroy. */
|
||||
|
|
|
@ -811,6 +811,10 @@ struct IOMMUMemoryRegion {
|
|||
#define IOMMU_NOTIFIER_FOREACH(n, mr) \
|
||||
QLIST_FOREACH((n), &(mr)->iommu_notify, node)
|
||||
|
||||
#define MEMORY_LISTENER_PRIORITY_MIN 0
|
||||
#define MEMORY_LISTENER_PRIORITY_ACCEL 10
|
||||
#define MEMORY_LISTENER_PRIORITY_DEV_BACKEND 10
|
||||
|
||||
/**
|
||||
* struct MemoryListener: callbacks structure for updates to the physical memory map
|
||||
*
|
||||
|
|
|
@ -241,9 +241,6 @@ typedef struct SavedIOTLB {
|
|||
struct KVMState;
|
||||
struct kvm_run;
|
||||
|
||||
struct hax_vcpu_state;
|
||||
struct hvf_vcpu_state;
|
||||
|
||||
/* work queue */
|
||||
|
||||
/* The union type allows passing of 64 bit target pointers on 32 bit
|
||||
|
@ -309,6 +306,7 @@ struct qemu_work_item;
|
|||
* @next_cpu: Next CPU sharing TB cache.
|
||||
* @opaque: User data.
|
||||
* @mem_io_pc: Host Program Counter at which the memory was accessed.
|
||||
* @accel: Pointer to accelerator specific state.
|
||||
* @kvm_fd: vCPU file descriptor for KVM.
|
||||
* @work_mutex: Lock to prevent multiple access to @work_list.
|
||||
* @work_list: List of pending asynchronous work.
|
||||
|
@ -338,7 +336,6 @@ struct CPUState {
|
|||
|
||||
struct QemuThread *thread;
|
||||
#ifdef _WIN32
|
||||
HANDLE hThread;
|
||||
QemuSemaphore sem;
|
||||
#endif
|
||||
int thread_id;
|
||||
|
@ -424,6 +421,7 @@ struct CPUState {
|
|||
uint32_t can_do_io;
|
||||
int32_t exception_index;
|
||||
|
||||
AccelCPUState *accel;
|
||||
/* shared by kvm, hax and hvf */
|
||||
bool vcpu_dirty;
|
||||
|
||||
|
@ -443,10 +441,6 @@ struct CPUState {
|
|||
/* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
|
||||
bool prctl_unalign_sigbus;
|
||||
|
||||
struct hax_vcpu_state *hax_vcpu;
|
||||
|
||||
struct hvf_vcpu_state *hvf;
|
||||
|
||||
/* track IOMMUs whose translations we've cached in the TCG TLB */
|
||||
GArray *iommu_notifiers;
|
||||
};
|
||||
|
|
|
@ -86,4 +86,6 @@ struct ARMGICClass {
|
|||
DeviceRealize parent_realize;
|
||||
};
|
||||
|
||||
const char *gic_class_name(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -329,4 +329,14 @@ struct ARMGICv3CommonClass {
|
|||
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
|
||||
const MemoryRegionOps *ops);
|
||||
|
||||
/**
|
||||
* gicv3_class_name
|
||||
*
|
||||
* Return name of GICv3 class to use depending on whether KVM acceleration is
|
||||
* in use. May throw an error if the chosen implementation is not available.
|
||||
*
|
||||
* Returns: class name to use
|
||||
*/
|
||||
const char *gicv3_class_name(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -122,5 +122,14 @@ struct GICv3ITSCommonClass {
|
|||
void (*post_load)(GICv3ITSState *s);
|
||||
};
|
||||
|
||||
/**
|
||||
* its_class_name:
|
||||
*
|
||||
* Return the ITS class name to use depending on whether KVM acceleration
|
||||
* and KVM CAP_SIGNAL_MSI are supported
|
||||
*
|
||||
* Returns: class name to use or NULL
|
||||
*/
|
||||
const char *its_class_name(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
* Incomplete struct types
|
||||
* Please keep this list in case-insensitive alphabetical order.
|
||||
*/
|
||||
typedef struct AccelCPUState AccelCPUState;
|
||||
typedef struct AccelState AccelState;
|
||||
typedef struct AdapterInfo AdapterInfo;
|
||||
typedef struct AddressSpace AddressSpace;
|
||||
|
|
|
@ -19,6 +19,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/* header to be included in non-HAX-specific code */
|
||||
|
||||
#ifndef QEMU_HAX_H
|
||||
#define QEMU_HAX_H
|
||||
|
||||
|
|
|
@ -49,7 +49,7 @@ struct HVFState {
|
|||
};
|
||||
extern HVFState *hvf_state;
|
||||
|
||||
struct hvf_vcpu_state {
|
||||
struct AccelCPUState {
|
||||
uint64_t fd;
|
||||
void *exit;
|
||||
bool vtimer_masked;
|
||||
|
|
|
@ -11,9 +11,12 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/* header to be included in non-KVM-specific code */
|
||||
|
||||
#ifndef QEMU_KVM_H
|
||||
#define QEMU_KVM_H
|
||||
|
||||
#include "exec/memattrs.h"
|
||||
#include "qemu/accel.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
|
|
|
@ -7,6 +7,8 @@
|
|||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
/* header to be included in non-NVMM-specific code */
|
||||
|
||||
#ifndef QEMU_NVMM_H
|
||||
#define QEMU_NVMM_H
|
||||
|
||||
|
|
|
@ -5,6 +5,8 @@
|
|||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
/* header to be included in non-TCG-specific code */
|
||||
|
||||
#ifndef SYSEMU_TCG_H
|
||||
#define SYSEMU_TCG_H
|
||||
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
/* header to be included in non-WHPX-specific code */
|
||||
|
||||
#ifndef QEMU_WHPX_H
|
||||
#define QEMU_WHPX_H
|
||||
|
||||
|
|
|
@ -5,6 +5,8 @@
|
|||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
/* header to be included in non-Xen-specific code */
|
||||
|
||||
#ifndef SYSEMU_XEN_H
|
||||
#define SYSEMU_XEN_H
|
||||
|
||||
|
|
|
@ -661,8 +661,8 @@ endif
|
|||
if get_option('whpx').allowed() and targetos == 'windows'
|
||||
if get_option('whpx').enabled() and host_machine.cpu() != 'x86_64'
|
||||
error('WHPX requires 64-bit host')
|
||||
elif cc.has_header('WinHvPlatform.h', required: get_option('whpx')) and \
|
||||
cc.has_header('WinHvEmulation.h', required: get_option('whpx'))
|
||||
elif cc.has_header('winhvplatform.h', required: get_option('whpx')) and \
|
||||
cc.has_header('winhvemulation.h', required: get_option('whpx'))
|
||||
accelerators += 'CONFIG_WHPX'
|
||||
endif
|
||||
endif
|
||||
|
|
|
@ -961,6 +961,7 @@ struct ArchCPU {
|
|||
*/
|
||||
uint32_t kvm_target;
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
/* KVM init features for this CPU */
|
||||
uint32_t kvm_init_features[7];
|
||||
|
||||
|
@ -973,6 +974,7 @@ struct ArchCPU {
|
|||
|
||||
/* KVM steal time */
|
||||
OnOffAuto kvm_steal_time;
|
||||
#endif /* CONFIG_KVM */
|
||||
|
||||
/* Uniprocessor system with MP extensions */
|
||||
bool mp_is_up;
|
||||
|
|
|
@ -544,29 +544,29 @@ int hvf_get_registers(CPUState *cpu)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
|
||||
ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val);
|
||||
ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
|
||||
*(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
|
||||
assert_hvf_ok(ret);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
|
||||
ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
|
||||
ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg,
|
||||
&fpval);
|
||||
memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval));
|
||||
assert_hvf_ok(ret);
|
||||
}
|
||||
|
||||
val = 0;
|
||||
ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val);
|
||||
ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val);
|
||||
assert_hvf_ok(ret);
|
||||
vfp_set_fpcr(env, val);
|
||||
|
||||
val = 0;
|
||||
ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val);
|
||||
ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val);
|
||||
assert_hvf_ok(ret);
|
||||
vfp_set_fpsr(env, val);
|
||||
|
||||
ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val);
|
||||
ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val);
|
||||
assert_hvf_ok(ret);
|
||||
pstate_write(env, val);
|
||||
|
||||
|
@ -575,7 +575,7 @@ int hvf_get_registers(CPUState *cpu)
|
|||
continue;
|
||||
}
|
||||
|
||||
if (cpu->hvf->guest_debug_enabled) {
|
||||
if (cpu->accel->guest_debug_enabled) {
|
||||
/* Handle debug registers */
|
||||
switch (hvf_sreg_match[i].reg) {
|
||||
case HV_SYS_REG_DBGBVR0_EL1:
|
||||
|
@ -661,7 +661,7 @@ int hvf_get_registers(CPUState *cpu)
|
|||
}
|
||||
}
|
||||
|
||||
ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);
|
||||
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
|
||||
|
@ -684,24 +684,24 @@ int hvf_put_registers(CPUState *cpu)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
|
||||
val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
|
||||
ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val);
|
||||
ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val);
|
||||
assert_hvf_ok(ret);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
|
||||
memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval));
|
||||
ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
|
||||
ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg,
|
||||
fpval);
|
||||
assert_hvf_ok(ret);
|
||||
}
|
||||
|
||||
ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env));
|
||||
ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env));
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env));
|
||||
ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env));
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env));
|
||||
ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env));
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
aarch64_save_sp(env, arm_current_el(env));
|
||||
|
@ -712,7 +712,7 @@ int hvf_put_registers(CPUState *cpu)
|
|||
continue;
|
||||
}
|
||||
|
||||
if (cpu->hvf->guest_debug_enabled) {
|
||||
if (cpu->accel->guest_debug_enabled) {
|
||||
/* Handle debug registers */
|
||||
switch (hvf_sreg_match[i].reg) {
|
||||
case HV_SYS_REG_DBGBVR0_EL1:
|
||||
|
@ -789,11 +789,11 @@ int hvf_put_registers(CPUState *cpu)
|
|||
}
|
||||
|
||||
val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
|
||||
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
|
||||
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val);
|
||||
assert_hvf_ok(ret);
|
||||
}
|
||||
|
||||
ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset);
|
||||
ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
return 0;
|
||||
|
@ -814,7 +814,7 @@ static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)
|
|||
flush_cpu_state(cpu);
|
||||
|
||||
if (rt < 31) {
|
||||
r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val);
|
||||
r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
}
|
||||
|
@ -827,7 +827,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt)
|
|||
flush_cpu_state(cpu);
|
||||
|
||||
if (rt < 31) {
|
||||
r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val);
|
||||
r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
|
||||
|
@ -969,22 +969,22 @@ int hvf_arch_init_vcpu(CPUState *cpu)
|
|||
assert(write_cpustate_to_list(arm_cpu, false));
|
||||
|
||||
/* Set CP_NO_RAW system registers on init */
|
||||
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,
|
||||
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1,
|
||||
arm_cpu->midr);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,
|
||||
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1,
|
||||
arm_cpu->mp_affinity);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
|
||||
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
|
||||
assert_hvf_ok(ret);
|
||||
pfr |= env->gicv3state ? (1 << 24) : 0;
|
||||
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
|
||||
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
/* We're limited to underlying hardware caps, override internal versions */
|
||||
ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
|
||||
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
|
||||
&arm_cpu->isar.id_aa64mmfr0);
|
||||
assert_hvf_ok(ret);
|
||||
|
||||
|
@ -994,7 +994,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)
|
|||
void hvf_kick_vcpu_thread(CPUState *cpu)
|
||||
{
|
||||
cpus_kick_thread(cpu);
|
||||
hv_vcpus_exit(&cpu->hvf->fd, 1);
|
||||
hv_vcpus_exit(&cpu->accel->fd, 1);
|
||||
}
|
||||
|
||||
static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
|
||||
|
@ -1678,13 +1678,13 @@ static int hvf_inject_interrupts(CPUState *cpu)
|
|||
{
|
||||
if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {
|
||||
trace_hvf_inject_fiq();
|
||||
hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ,
|
||||
hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ,
|
||||
true);
|
||||
}
|
||||
|
||||
if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
trace_hvf_inject_irq();
|
||||
hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ,
|
||||
hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ,
|
||||
true);
|
||||
}
|
||||
|
||||
|
@ -1718,7 +1718,7 @@ static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts)
|
|||
*/
|
||||
qatomic_set_mb(&cpu->thread_kicked, false);
|
||||
qemu_mutex_unlock_iothread();
|
||||
pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask);
|
||||
pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask);
|
||||
qemu_mutex_lock_iothread();
|
||||
}
|
||||
|
||||
|
@ -1739,7 +1739,7 @@ static void hvf_wfi(CPUState *cpu)
|
|||
return;
|
||||
}
|
||||
|
||||
r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
|
||||
r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
if (!(ctl & 1) || (ctl & 2)) {
|
||||
|
@ -1748,7 +1748,7 @@ static void hvf_wfi(CPUState *cpu)
|
|||
return;
|
||||
}
|
||||
|
||||
r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
|
||||
r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
ticks_to_sleep = cval - hvf_vtimer_val();
|
||||
|
@ -1781,12 +1781,12 @@ static void hvf_sync_vtimer(CPUState *cpu)
|
|||
uint64_t ctl;
|
||||
bool irq_state;
|
||||
|
||||
if (!cpu->hvf->vtimer_masked) {
|
||||
if (!cpu->accel->vtimer_masked) {
|
||||
/* We will get notified on vtimer changes by hvf, nothing to do */
|
||||
return;
|
||||
}
|
||||
|
||||
r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
|
||||
r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) ==
|
||||
|
@ -1795,8 +1795,8 @@ static void hvf_sync_vtimer(CPUState *cpu)
|
|||
|
||||
if (!irq_state) {
|
||||
/* Timer no longer asserting, we can unmask it */
|
||||
hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);
|
||||
cpu->hvf->vtimer_masked = false;
|
||||
hv_vcpu_set_vtimer_mask(cpu->accel->fd, false);
|
||||
cpu->accel->vtimer_masked = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1805,7 +1805,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
ARMCPU *arm_cpu = ARM_CPU(cpu);
|
||||
CPUARMState *env = &arm_cpu->env;
|
||||
int ret;
|
||||
hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;
|
||||
hv_vcpu_exit_t *hvf_exit = cpu->accel->exit;
|
||||
hv_return_t r;
|
||||
bool advance_pc = false;
|
||||
|
||||
|
@ -1821,7 +1821,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
flush_cpu_state(cpu);
|
||||
|
||||
qemu_mutex_unlock_iothread();
|
||||
assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd));
|
||||
assert_hvf_ok(hv_vcpu_run(cpu->accel->fd));
|
||||
|
||||
/* handle VMEXIT */
|
||||
uint64_t exit_reason = hvf_exit->reason;
|
||||
|
@ -1836,7 +1836,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
break;
|
||||
case HV_EXIT_REASON_VTIMER_ACTIVATED:
|
||||
qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
|
||||
cpu->hvf->vtimer_masked = true;
|
||||
cpu->accel->vtimer_masked = true;
|
||||
return 0;
|
||||
case HV_EXIT_REASON_CANCELED:
|
||||
/* we got kicked, no exit to process */
|
||||
|
@ -1990,10 +1990,10 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
|
||||
flush_cpu_state(cpu);
|
||||
|
||||
r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc);
|
||||
r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc);
|
||||
assert_hvf_ok(r);
|
||||
pc += 4;
|
||||
r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc);
|
||||
r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
/* Handle single-stepping over instructions which trigger a VM exit */
|
||||
|
@ -2113,29 +2113,29 @@ static void hvf_put_gdbstub_debug_registers(CPUState *cpu)
|
|||
|
||||
for (i = 0; i < cur_hw_bps; i++) {
|
||||
HWBreakpoint *bp = get_hw_bp(i);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], bp->bcr);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], bp->bvr);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
for (i = cur_hw_bps; i < max_hw_bps; i++) {
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i], 0);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i], 0);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
|
||||
for (i = 0; i < cur_hw_wps; i++) {
|
||||
HWWatchpoint *wp = get_hw_wp(i);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], wp->wcr);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], wp->wvr);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
for (i = cur_hw_wps; i < max_hw_wps; i++) {
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i], 0);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i], 0);
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
}
|
||||
|
@ -2152,19 +2152,19 @@ static void hvf_put_guest_debug_registers(CPUState *cpu)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < max_hw_bps; i++) {
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbcr_regs[i],
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i],
|
||||
env->cp15.dbgbcr[i]);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgbvr_regs[i],
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i],
|
||||
env->cp15.dbgbvr[i]);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
|
||||
for (i = 0; i < max_hw_wps; i++) {
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwcr_regs[i],
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i],
|
||||
env->cp15.dbgwcr[i]);
|
||||
assert_hvf_ok(r);
|
||||
r = hv_vcpu_set_sys_reg(cpu->hvf->fd, dbgwvr_regs[i],
|
||||
r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i],
|
||||
env->cp15.dbgwvr[i]);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
|
@ -2184,16 +2184,16 @@ static void hvf_arch_set_traps(void)
|
|||
/* Check whether guest debugging is enabled for at least one vCPU; if it
|
||||
* is, enable exiting the guest on all vCPUs */
|
||||
CPU_FOREACH(cpu) {
|
||||
should_enable_traps |= cpu->hvf->guest_debug_enabled;
|
||||
should_enable_traps |= cpu->accel->guest_debug_enabled;
|
||||
}
|
||||
CPU_FOREACH(cpu) {
|
||||
/* Set whether debug exceptions exit the guest */
|
||||
r = hv_vcpu_set_trap_debug_exceptions(cpu->hvf->fd,
|
||||
r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
|
||||
should_enable_traps);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
/* Set whether accesses to debug registers exit the guest */
|
||||
r = hv_vcpu_set_trap_debug_reg_accesses(cpu->hvf->fd,
|
||||
r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
|
||||
should_enable_traps);
|
||||
assert_hvf_ok(r);
|
||||
}
|
||||
|
@ -2205,12 +2205,12 @@ void hvf_arch_update_guest_debug(CPUState *cpu)
|
|||
CPUARMState *env = &arm_cpu->env;
|
||||
|
||||
/* Check whether guest debugging is enabled */
|
||||
cpu->hvf->guest_debug_enabled = cpu->singlestep_enabled ||
|
||||
cpu->accel->guest_debug_enabled = cpu->singlestep_enabled ||
|
||||
hvf_sw_breakpoints_active(cpu) ||
|
||||
hvf_arm_hw_debug_active(cpu);
|
||||
|
||||
/* Update debug registers */
|
||||
if (cpu->hvf->guest_debug_enabled) {
|
||||
if (cpu->accel->guest_debug_enabled) {
|
||||
hvf_put_gdbstub_debug_registers(cpu);
|
||||
} else {
|
||||
hvf_put_guest_debug_registers(cpu);
|
||||
|
|
|
@ -341,6 +341,7 @@ static MemoryListener devlistener = {
|
|||
.name = "kvm-arm",
|
||||
.region_add = kvm_arm_devlistener_add,
|
||||
.region_del = kvm_arm_devlistener_del,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_MIN,
|
||||
};
|
||||
|
||||
static void kvm_arm_set_device_addr(KVMDevice *kd)
|
||||
|
|
|
@ -453,32 +453,6 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs)
|
|||
|
||||
#endif
|
||||
|
||||
static inline const char *gic_class_name(void)
|
||||
{
|
||||
return kvm_irqchip_in_kernel() ? "kvm-arm-gic" : "arm_gic";
|
||||
}
|
||||
|
||||
/**
|
||||
* gicv3_class_name
|
||||
*
|
||||
* Return name of GICv3 class to use depending on whether KVM acceleration is
|
||||
* in use. May throw an error if the chosen implementation is not available.
|
||||
*
|
||||
* Returns: class name to use
|
||||
*/
|
||||
static inline const char *gicv3_class_name(void)
|
||||
{
|
||||
if (kvm_irqchip_in_kernel()) {
|
||||
return "kvm-arm-gicv3";
|
||||
} else {
|
||||
if (kvm_enabled()) {
|
||||
error_report("Userspace GICv3 is not supported with KVM");
|
||||
exit(1);
|
||||
}
|
||||
return "arm-gicv3";
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_arm_handle_debug:
|
||||
* @cs: CPUState
|
||||
|
@ -516,23 +490,4 @@ void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
|
|||
*/
|
||||
bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
|
||||
|
||||
/**
|
||||
* its_class_name:
|
||||
*
|
||||
* Return the ITS class name to use depending on whether KVM acceleration
|
||||
* and KVM CAP_SIGNAL_MSI are supported
|
||||
*
|
||||
* Returns: class name to use or NULL
|
||||
*/
|
||||
static inline const char *its_class_name(void)
|
||||
{
|
||||
if (kvm_irqchip_in_kernel()) {
|
||||
/* KVM implementation requires this capability */
|
||||
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
|
||||
} else {
|
||||
/* Software emulation based model */
|
||||
return "arm-gicv3-its";
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -53,6 +53,8 @@ static void *hax_cpu_thread_fn(void *arg)
|
|||
|
||||
qemu_wait_io_event(cpu);
|
||||
} while (!cpu->unplug || cpu_can_run(cpu));
|
||||
hax_vcpu_destroy(cpu);
|
||||
cpu_thread_signal_destroyed(cpu);
|
||||
rcu_unregister_thread();
|
||||
return NULL;
|
||||
}
|
||||
|
@ -69,8 +71,9 @@ static void hax_start_vcpu_thread(CPUState *cpu)
|
|||
cpu->cpu_index);
|
||||
qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn,
|
||||
cpu, QEMU_THREAD_JOINABLE);
|
||||
assert(cpu->accel);
|
||||
#ifdef _WIN32
|
||||
cpu->hThread = qemu_thread_get_handle(cpu->thread);
|
||||
cpu->accel->hThread = qemu_thread_get_handle(cpu->thread);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size)
|
|||
|
||||
hax_fd hax_vcpu_get_fd(CPUArchState *env)
|
||||
{
|
||||
struct hax_vcpu_state *vcpu = env_cpu(env)->hax_vcpu;
|
||||
AccelCPUState *vcpu = env_cpu(env)->accel;
|
||||
if (!vcpu) {
|
||||
return HAX_INVALID_FD;
|
||||
}
|
||||
|
@ -136,7 +136,7 @@ static int hax_version_support(struct hax_state *hax)
|
|||
|
||||
int hax_vcpu_create(int id)
|
||||
{
|
||||
struct hax_vcpu_state *vcpu = NULL;
|
||||
AccelCPUState *vcpu = NULL;
|
||||
int ret;
|
||||
|
||||
if (!hax_global.vm) {
|
||||
|
@ -149,7 +149,7 @@ int hax_vcpu_create(int id)
|
|||
return 0;
|
||||
}
|
||||
|
||||
vcpu = g_new0(struct hax_vcpu_state, 1);
|
||||
vcpu = g_new0(AccelCPUState, 1);
|
||||
|
||||
ret = hax_host_create_vcpu(hax_global.vm->fd, id);
|
||||
if (ret) {
|
||||
|
@ -188,7 +188,7 @@ int hax_vcpu_create(int id)
|
|||
|
||||
int hax_vcpu_destroy(CPUState *cpu)
|
||||
{
|
||||
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
|
||||
if (!hax_global.vm) {
|
||||
fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu_id);
|
||||
|
@ -205,7 +205,11 @@ int hax_vcpu_destroy(CPUState *cpu)
|
|||
*/
|
||||
hax_close_fd(vcpu->fd);
|
||||
hax_global.vm->vcpus[vcpu->vcpu_id] = NULL;
|
||||
#ifdef _WIN32
|
||||
CloseHandle(vcpu->hThread);
|
||||
#endif
|
||||
g_free(vcpu);
|
||||
cpu->accel = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -219,7 +223,7 @@ int hax_init_vcpu(CPUState *cpu)
|
|||
exit(-1);
|
||||
}
|
||||
|
||||
cpu->hax_vcpu = hax_global.vm->vcpus[cpu->cpu_index];
|
||||
cpu->accel = hax_global.vm->vcpus[cpu->cpu_index];
|
||||
cpu->vcpu_dirty = true;
|
||||
qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr);
|
||||
|
||||
|
@ -259,7 +263,7 @@ struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus)
|
|||
}
|
||||
|
||||
vm->numvcpus = max_cpus;
|
||||
vm->vcpus = g_new0(struct hax_vcpu_state *, vm->numvcpus);
|
||||
vm->vcpus = g_new0(AccelCPUState *, vm->numvcpus);
|
||||
for (i = 0; i < vm->numvcpus; i++) {
|
||||
vm->vcpus[i] = NULL;
|
||||
}
|
||||
|
@ -411,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port,
|
|||
static int hax_vcpu_interrupt(CPUArchState *env)
|
||||
{
|
||||
CPUState *cpu = env_cpu(env);
|
||||
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
struct hax_tunnel *ht = vcpu->tunnel;
|
||||
|
||||
/*
|
||||
|
@ -443,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env)
|
|||
|
||||
void hax_raise_event(CPUState *cpu)
|
||||
{
|
||||
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
|
||||
if (!vcpu) {
|
||||
return;
|
||||
|
@ -464,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env)
|
|||
int ret = 0;
|
||||
CPUState *cpu = env_cpu(env);
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct hax_vcpu_state *vcpu = cpu->hax_vcpu;
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
struct hax_tunnel *ht = vcpu->tunnel;
|
||||
|
||||
if (!hax_enabled()) {
|
||||
|
@ -1110,8 +1114,8 @@ void hax_reset_vcpu_state(void *opaque)
|
|||
{
|
||||
CPUState *cpu;
|
||||
for (cpu = first_cpu; cpu != NULL; cpu = CPU_NEXT(cpu)) {
|
||||
cpu->hax_vcpu->tunnel->user_event_pending = 0;
|
||||
cpu->hax_vcpu->tunnel->ready_for_interrupt_injection = 0;
|
||||
cpu->accel->tunnel->user_event_pending = 0;
|
||||
cpu->accel->tunnel->ready_for_interrupt_injection = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -25,7 +25,11 @@ typedef HANDLE hax_fd;
|
|||
#endif
|
||||
|
||||
extern struct hax_state hax_global;
|
||||
struct hax_vcpu_state {
|
||||
|
||||
struct AccelCPUState {
|
||||
#ifdef _WIN32
|
||||
HANDLE hThread;
|
||||
#endif
|
||||
hax_fd fd;
|
||||
int vcpu_id;
|
||||
struct hax_tunnel *tunnel;
|
||||
|
@ -46,7 +50,7 @@ struct hax_vm {
|
|||
hax_fd fd;
|
||||
int id;
|
||||
int numvcpus;
|
||||
struct hax_vcpu_state **vcpus;
|
||||
AccelCPUState **vcpus;
|
||||
};
|
||||
|
||||
/* Functions exported to host specific mode */
|
||||
|
@ -57,7 +61,7 @@ int valid_hax_tunnel_size(uint16_t size);
|
|||
int hax_mod_version(struct hax_state *hax, struct hax_module_version *version);
|
||||
int hax_inject_interrupt(CPUArchState *env, int vector);
|
||||
struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus);
|
||||
int hax_vcpu_run(struct hax_vcpu_state *vcpu);
|
||||
int hax_vcpu_run(AccelCPUState *vcpu);
|
||||
int hax_vcpu_create(int id);
|
||||
void hax_kick_vcpu_thread(CPUState *cpu);
|
||||
|
||||
|
@ -76,7 +80,7 @@ int hax_host_create_vm(struct hax_state *hax, int *vm_id);
|
|||
hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id);
|
||||
int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid);
|
||||
hax_fd hax_host_open_vcpu(int vmid, int vcpuid);
|
||||
int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu);
|
||||
int hax_host_setup_vcpu_channel(AccelCPUState *vcpu);
|
||||
hax_fd hax_mod_open(void);
|
||||
void hax_memory_init(void);
|
||||
|
||||
|
|
|
@ -291,7 +291,7 @@ static MemoryListener hax_memory_listener = {
|
|||
.region_add = hax_region_add,
|
||||
.region_del = hax_region_del,
|
||||
.log_sync = hax_log_sync,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
static void hax_ram_block_added(RAMBlockNotifier *n, void *host, size_t size,
|
||||
|
|
|
@ -205,7 +205,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid)
|
|||
return fd;
|
||||
}
|
||||
|
||||
int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu)
|
||||
int hax_host_setup_vcpu_channel(AccelCPUState *vcpu)
|
||||
{
|
||||
int ret;
|
||||
struct hax_tunnel_info info;
|
||||
|
@ -227,7 +227,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int hax_vcpu_run(struct hax_vcpu_state *vcpu)
|
||||
int hax_vcpu_run(AccelCPUState *vcpu)
|
||||
{
|
||||
return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL);
|
||||
}
|
||||
|
|
|
@ -301,7 +301,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid)
|
|||
return hDeviceVCPU;
|
||||
}
|
||||
|
||||
int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu)
|
||||
int hax_host_setup_vcpu_channel(AccelCPUState *vcpu)
|
||||
{
|
||||
hax_fd hDeviceVCPU = vcpu->fd;
|
||||
int ret;
|
||||
|
@ -327,7 +327,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int hax_vcpu_run(struct hax_vcpu_state *vcpu)
|
||||
int hax_vcpu_run(AccelCPUState *vcpu)
|
||||
{
|
||||
int ret;
|
||||
HANDLE hDeviceVCPU = vcpu->fd;
|
||||
|
@ -476,7 +476,7 @@ void hax_kick_vcpu_thread(CPUState *cpu)
|
|||
*/
|
||||
cpu->exit_request = 1;
|
||||
if (!qemu_cpu_is_self(cpu)) {
|
||||
if (!QueueUserAPC(dummy_apc_func, cpu->hThread, 0)) {
|
||||
if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) {
|
||||
fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n",
|
||||
__func__, GetLastError());
|
||||
exit(1);
|
||||
|
|
|
@ -81,11 +81,11 @@ void vmx_update_tpr(CPUState *cpu)
|
|||
int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
|
||||
int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
|
||||
|
||||
wreg(cpu->hvf->fd, HV_X86_TPR, tpr);
|
||||
wreg(cpu->accel->fd, HV_X86_TPR, tpr);
|
||||
if (irr == -1) {
|
||||
wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
|
||||
wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0);
|
||||
} else {
|
||||
wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
|
||||
wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
|
||||
irr >> 4);
|
||||
}
|
||||
}
|
||||
|
@ -93,7 +93,7 @@ void vmx_update_tpr(CPUState *cpu)
|
|||
static void update_apic_tpr(CPUState *cpu)
|
||||
{
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4;
|
||||
int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4;
|
||||
cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
|
||||
}
|
||||
|
||||
|
@ -256,12 +256,12 @@ int hvf_arch_init_vcpu(CPUState *cpu)
|
|||
}
|
||||
|
||||
/* set VMCS control fields */
|
||||
wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,
|
||||
wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS,
|
||||
cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
|
||||
VMCS_PIN_BASED_CTLS_EXTINT |
|
||||
VMCS_PIN_BASED_CTLS_NMI |
|
||||
VMCS_PIN_BASED_CTLS_VNMI));
|
||||
wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,
|
||||
wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS,
|
||||
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
|
||||
VMCS_PRI_PROC_BASED_CTLS_HLT |
|
||||
VMCS_PRI_PROC_BASED_CTLS_MWAIT |
|
||||
|
@ -276,14 +276,14 @@ int hvf_arch_init_vcpu(CPUState *cpu)
|
|||
reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP;
|
||||
}
|
||||
|
||||
wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,
|
||||
wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS,
|
||||
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap));
|
||||
|
||||
wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
|
||||
0));
|
||||
wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
|
||||
wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS,
|
||||
cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0));
|
||||
wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
|
||||
|
||||
wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
|
||||
wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0);
|
||||
|
||||
x86cpu = X86_CPU(cpu);
|
||||
x86cpu->env.xsave_buf_len = 4096;
|
||||
|
@ -295,18 +295,18 @@ int hvf_arch_init_vcpu(CPUState *cpu)
|
|||
*/
|
||||
assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len);
|
||||
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1);
|
||||
hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -347,16 +347,16 @@ static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_in
|
|||
}
|
||||
if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {
|
||||
env->has_error_code = true;
|
||||
env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR);
|
||||
env->error_code = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_ERROR);
|
||||
}
|
||||
}
|
||||
if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
||||
if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
||||
VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {
|
||||
env->hflags2 |= HF2_NMI_MASK;
|
||||
} else {
|
||||
env->hflags2 &= ~HF2_NMI_MASK;
|
||||
}
|
||||
if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
||||
if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
||||
(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
|
||||
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
|
||||
env->hflags |= HF_INHIBIT_IRQ_MASK;
|
||||
|
@ -435,20 +435,20 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
return EXCP_HLT;
|
||||
}
|
||||
|
||||
hv_return_t r = hv_vcpu_run(cpu->hvf->fd);
|
||||
hv_return_t r = hv_vcpu_run(cpu->accel->fd);
|
||||
assert_hvf_ok(r);
|
||||
|
||||
/* handle VMEXIT */
|
||||
uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON);
|
||||
uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION);
|
||||
uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd,
|
||||
uint64_t exit_reason = rvmcs(cpu->accel->fd, VMCS_EXIT_REASON);
|
||||
uint64_t exit_qual = rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATION);
|
||||
uint32_t ins_len = (uint32_t)rvmcs(cpu->accel->fd,
|
||||
VMCS_EXIT_INSTRUCTION_LENGTH);
|
||||
|
||||
uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
|
||||
uint64_t idtvec_info = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO);
|
||||
|
||||
hvf_store_events(cpu, ins_len, idtvec_info);
|
||||
rip = rreg(cpu->hvf->fd, HV_X86_RIP);
|
||||
env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);
|
||||
rip = rreg(cpu->accel->fd, HV_X86_RIP);
|
||||
env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
|
||||
|
||||
qemu_mutex_lock_iothread();
|
||||
|
||||
|
@ -478,7 +478,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
case EXIT_REASON_EPT_FAULT:
|
||||
{
|
||||
hvf_slot *slot;
|
||||
uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS);
|
||||
uint64_t gpa = rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADDRESS);
|
||||
|
||||
if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&
|
||||
((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {
|
||||
|
@ -523,7 +523,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
store_regs(cpu);
|
||||
break;
|
||||
} else if (!string && !in) {
|
||||
RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX);
|
||||
RAX(env) = rreg(cpu->accel->fd, HV_X86_RAX);
|
||||
hvf_handle_io(env, port, &RAX(env), 1, size, 1);
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
break;
|
||||
|
@ -539,21 +539,21 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
break;
|
||||
}
|
||||
case EXIT_REASON_CPUID: {
|
||||
uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
|
||||
uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX);
|
||||
uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
|
||||
uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
|
||||
uint32_t rax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX);
|
||||
uint32_t rbx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX);
|
||||
uint32_t rcx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX);
|
||||
uint32_t rdx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX);
|
||||
|
||||
if (rax == 1) {
|
||||
/* CPUID1.ecx.OSXSAVE needs to know CR4 */
|
||||
env->cr[4] = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);
|
||||
env->cr[4] = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4);
|
||||
}
|
||||
hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);
|
||||
|
||||
wreg(cpu->hvf->fd, HV_X86_RAX, rax);
|
||||
wreg(cpu->hvf->fd, HV_X86_RBX, rbx);
|
||||
wreg(cpu->hvf->fd, HV_X86_RCX, rcx);
|
||||
wreg(cpu->hvf->fd, HV_X86_RDX, rdx);
|
||||
wreg(cpu->accel->fd, HV_X86_RAX, rax);
|
||||
wreg(cpu->accel->fd, HV_X86_RBX, rbx);
|
||||
wreg(cpu->accel->fd, HV_X86_RCX, rcx);
|
||||
wreg(cpu->accel->fd, HV_X86_RDX, rdx);
|
||||
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
break;
|
||||
|
@ -561,16 +561,16 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
case EXIT_REASON_XSETBV: {
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
CPUX86State *env = &x86_cpu->env;
|
||||
uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
|
||||
uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
|
||||
uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
|
||||
uint32_t eax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX);
|
||||
uint32_t ecx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX);
|
||||
uint32_t edx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX);
|
||||
|
||||
if (ecx) {
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
break;
|
||||
}
|
||||
env->xcr0 = ((uint64_t)edx << 32) | eax;
|
||||
wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1);
|
||||
wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1);
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
break;
|
||||
}
|
||||
|
@ -609,11 +609,11 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
|
||||
switch (cr) {
|
||||
case 0x0: {
|
||||
macvm_set_cr0(cpu->hvf->fd, RRX(env, reg));
|
||||
macvm_set_cr0(cpu->accel->fd, RRX(env, reg));
|
||||
break;
|
||||
}
|
||||
case 4: {
|
||||
macvm_set_cr4(cpu->hvf->fd, RRX(env, reg));
|
||||
macvm_set_cr4(cpu->accel->fd, RRX(env, reg));
|
||||
break;
|
||||
}
|
||||
case 8: {
|
||||
|
@ -649,7 +649,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
break;
|
||||
}
|
||||
case EXIT_REASON_TASK_SWITCH: {
|
||||
uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
|
||||
uint64_t vinfo = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO);
|
||||
x68_segment_selector sel = {.sel = exit_qual & 0xffff};
|
||||
vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
|
||||
vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
|
||||
|
@ -662,8 +662,8 @@ int hvf_vcpu_exec(CPUState *cpu)
|
|||
break;
|
||||
}
|
||||
case EXIT_REASON_RDPMC:
|
||||
wreg(cpu->hvf->fd, HV_X86_RAX, 0);
|
||||
wreg(cpu->hvf->fd, HV_X86_RDX, 0);
|
||||
wreg(cpu->accel->fd, HV_X86_RAX, 0);
|
||||
wreg(cpu->accel->fd, HV_X86_RDX, 0);
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
break;
|
||||
case VMX_REASON_VMCALL:
|
||||
|
|
|
@ -180,15 +180,15 @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)
|
|||
uint64_t val;
|
||||
|
||||
/* BUG, should take considering overlap.. */
|
||||
wreg(cpu->hvf->fd, HV_X86_RIP, rip);
|
||||
wreg(cpu->accel->fd, HV_X86_RIP, rip);
|
||||
env->eip = rip;
|
||||
|
||||
/* after moving forward in rip, we need to clean INTERRUPTABILITY */
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
val = rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
|
||||
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
|
||||
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY,
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY,
|
||||
val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
|
||||
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
|
||||
}
|
||||
|
@ -200,9 +200,9 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu)
|
|||
CPUX86State *env = &x86_cpu->env;
|
||||
|
||||
env->hflags2 &= ~HF2_NMI_MASK;
|
||||
uint32_t gi = (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
uint32_t gi = (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
|
||||
}
|
||||
|
||||
static inline void vmx_set_nmi_blocking(CPUState *cpu)
|
||||
|
@ -211,16 +211,16 @@ static inline void vmx_set_nmi_blocking(CPUState *cpu)
|
|||
CPUX86State *env = &x86_cpu->env;
|
||||
|
||||
env->hflags2 |= HF2_NMI_MASK;
|
||||
uint32_t gi = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
uint32_t gi = (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY);
|
||||
gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
|
||||
}
|
||||
|
||||
static inline void vmx_set_nmi_window_exiting(CPUState *cpu)
|
||||
{
|
||||
uint64_t val;
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |
|
||||
val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val |
|
||||
VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
|
||||
|
||||
}
|
||||
|
@ -229,8 +229,8 @@ static inline void vmx_clear_nmi_window_exiting(CPUState *cpu)
|
|||
{
|
||||
|
||||
uint64_t val;
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &
|
||||
val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val &
|
||||
~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
|
||||
}
|
||||
|
||||
|
|
|
@ -61,11 +61,11 @@ bool x86_read_segment_descriptor(struct CPUState *cpu,
|
|||
}
|
||||
|
||||
if (GDT_SEL == sel.ti) {
|
||||
base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);
|
||||
limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE);
|
||||
limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
} else {
|
||||
base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);
|
||||
limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);
|
||||
base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE);
|
||||
limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT);
|
||||
}
|
||||
|
||||
if (sel.index * 8 >= limit) {
|
||||
|
@ -84,11 +84,11 @@ bool x86_write_segment_descriptor(struct CPUState *cpu,
|
|||
uint32_t limit;
|
||||
|
||||
if (GDT_SEL == sel.ti) {
|
||||
base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);
|
||||
limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE);
|
||||
limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
} else {
|
||||
base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);
|
||||
limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);
|
||||
base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE);
|
||||
limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT);
|
||||
}
|
||||
|
||||
if (sel.index * 8 >= limit) {
|
||||
|
@ -102,8 +102,8 @@ bool x86_write_segment_descriptor(struct CPUState *cpu,
|
|||
bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
|
||||
int gate)
|
||||
{
|
||||
target_ulong base = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE);
|
||||
uint32_t limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT);
|
||||
target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE);
|
||||
uint32_t limit = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT);
|
||||
|
||||
memset(idt_desc, 0, sizeof(*idt_desc));
|
||||
if (gate * 8 >= limit) {
|
||||
|
@ -117,7 +117,7 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
|
|||
|
||||
bool x86_is_protected(struct CPUState *cpu)
|
||||
{
|
||||
uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
|
||||
uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0);
|
||||
return cr0 & CR0_PE_MASK;
|
||||
}
|
||||
|
||||
|
@ -135,7 +135,7 @@ bool x86_is_v8086(struct CPUState *cpu)
|
|||
|
||||
bool x86_is_long_mode(struct CPUState *cpu)
|
||||
{
|
||||
return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;
|
||||
return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;
|
||||
}
|
||||
|
||||
bool x86_is_long64_mode(struct CPUState *cpu)
|
||||
|
@ -148,13 +148,13 @@ bool x86_is_long64_mode(struct CPUState *cpu)
|
|||
|
||||
bool x86_is_paging_mode(struct CPUState *cpu)
|
||||
{
|
||||
uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
|
||||
uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0);
|
||||
return cr0 & CR0_PG_MASK;
|
||||
}
|
||||
|
||||
bool x86_is_pae_enabled(struct CPUState *cpu)
|
||||
{
|
||||
uint64_t cr4 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);
|
||||
uint64_t cr4 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4);
|
||||
return cr4 & CR4_PAE_MASK;
|
||||
}
|
||||
|
||||
|
|
|
@ -47,47 +47,47 @@ static const struct vmx_segment_field {
|
|||
|
||||
uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg)
|
||||
{
|
||||
return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);
|
||||
return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit);
|
||||
}
|
||||
|
||||
uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg)
|
||||
{
|
||||
return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);
|
||||
return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes);
|
||||
}
|
||||
|
||||
uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg)
|
||||
{
|
||||
return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);
|
||||
return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base);
|
||||
}
|
||||
|
||||
x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg)
|
||||
{
|
||||
x68_segment_selector sel;
|
||||
sel.sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);
|
||||
sel.sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector);
|
||||
return sel;
|
||||
}
|
||||
|
||||
void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg)
|
||||
{
|
||||
wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel);
|
||||
wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel);
|
||||
}
|
||||
|
||||
void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
|
||||
{
|
||||
desc->sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);
|
||||
desc->base = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);
|
||||
desc->limit = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);
|
||||
desc->ar = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);
|
||||
desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector);
|
||||
desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base);
|
||||
desc->limit = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit);
|
||||
desc->ar = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes);
|
||||
}
|
||||
|
||||
void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg)
|
||||
{
|
||||
const struct vmx_segment_field *sf = &vmx_segment_fields[seg];
|
||||
|
||||
wvmcs(cpu->hvf->fd, sf->base, desc->base);
|
||||
wvmcs(cpu->hvf->fd, sf->limit, desc->limit);
|
||||
wvmcs(cpu->hvf->fd, sf->selector, desc->sel);
|
||||
wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar);
|
||||
wvmcs(cpu->accel->fd, sf->base, desc->base);
|
||||
wvmcs(cpu->accel->fd, sf->limit, desc->limit);
|
||||
wvmcs(cpu->accel->fd, sf->selector, desc->sel);
|
||||
wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar);
|
||||
}
|
||||
|
||||
void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)
|
||||
|
|
|
@ -673,7 +673,7 @@ void simulate_rdmsr(struct CPUState *cpu)
|
|||
|
||||
switch (msr) {
|
||||
case MSR_IA32_TSC:
|
||||
val = rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET);
|
||||
val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET);
|
||||
break;
|
||||
case MSR_IA32_APICBASE:
|
||||
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
|
||||
|
@ -682,16 +682,16 @@ void simulate_rdmsr(struct CPUState *cpu)
|
|||
val = x86_cpu->ucode_rev;
|
||||
break;
|
||||
case MSR_EFER:
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER);
|
||||
val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER);
|
||||
break;
|
||||
case MSR_FSBASE:
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE);
|
||||
val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE);
|
||||
break;
|
||||
case MSR_GSBASE:
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE);
|
||||
val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE);
|
||||
break;
|
||||
case MSR_KERNELGSBASE:
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE);
|
||||
val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE);
|
||||
break;
|
||||
case MSR_STAR:
|
||||
abort();
|
||||
|
@ -779,13 +779,13 @@ void simulate_wrmsr(struct CPUState *cpu)
|
|||
cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
|
||||
break;
|
||||
case MSR_FSBASE:
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);
|
||||
break;
|
||||
case MSR_GSBASE:
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data);
|
||||
break;
|
||||
case MSR_KERNELGSBASE:
|
||||
wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data);
|
||||
wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data);
|
||||
break;
|
||||
case MSR_STAR:
|
||||
abort();
|
||||
|
@ -798,9 +798,9 @@ void simulate_wrmsr(struct CPUState *cpu)
|
|||
break;
|
||||
case MSR_EFER:
|
||||
/*printf("new efer %llx\n", EFER(cpu));*/
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data);
|
||||
if (data & MSR_EFER_NXE) {
|
||||
hv_vcpu_invalidate_tlb(cpu->hvf->fd);
|
||||
hv_vcpu_invalidate_tlb(cpu->accel->fd);
|
||||
}
|
||||
break;
|
||||
case MSR_MTRRphysBase(0):
|
||||
|
@ -1424,21 +1424,21 @@ void load_regs(struct CPUState *cpu)
|
|||
CPUX86State *env = &x86_cpu->env;
|
||||
|
||||
int i = 0;
|
||||
RRX(env, R_EAX) = rreg(cpu->hvf->fd, HV_X86_RAX);
|
||||
RRX(env, R_EBX) = rreg(cpu->hvf->fd, HV_X86_RBX);
|
||||
RRX(env, R_ECX) = rreg(cpu->hvf->fd, HV_X86_RCX);
|
||||
RRX(env, R_EDX) = rreg(cpu->hvf->fd, HV_X86_RDX);
|
||||
RRX(env, R_ESI) = rreg(cpu->hvf->fd, HV_X86_RSI);
|
||||
RRX(env, R_EDI) = rreg(cpu->hvf->fd, HV_X86_RDI);
|
||||
RRX(env, R_ESP) = rreg(cpu->hvf->fd, HV_X86_RSP);
|
||||
RRX(env, R_EBP) = rreg(cpu->hvf->fd, HV_X86_RBP);
|
||||
RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX);
|
||||
RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX);
|
||||
RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX);
|
||||
RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX);
|
||||
RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI);
|
||||
RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI);
|
||||
RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP);
|
||||
RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP);
|
||||
for (i = 8; i < 16; i++) {
|
||||
RRX(env, i) = rreg(cpu->hvf->fd, HV_X86_RAX + i);
|
||||
RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i);
|
||||
}
|
||||
|
||||
env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);
|
||||
env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS);
|
||||
rflags_to_lflags(env);
|
||||
env->eip = rreg(cpu->hvf->fd, HV_X86_RIP);
|
||||
env->eip = rreg(cpu->accel->fd, HV_X86_RIP);
|
||||
}
|
||||
|
||||
void store_regs(struct CPUState *cpu)
|
||||
|
@ -1447,20 +1447,20 @@ void store_regs(struct CPUState *cpu)
|
|||
CPUX86State *env = &x86_cpu->env;
|
||||
|
||||
int i = 0;
|
||||
wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env));
|
||||
wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RAX, RAX(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RBX, RBX(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RCX, RCX(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RDX, RDX(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RSI, RSI(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RDI, RDI(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RBP, RBP(env));
|
||||
wreg(cpu->accel->fd, HV_X86_RSP, RSP(env));
|
||||
for (i = 8; i < 16; i++) {
|
||||
wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i));
|
||||
wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i));
|
||||
}
|
||||
|
||||
lflags_to_rflags(env);
|
||||
wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags);
|
||||
wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags);
|
||||
macvm_set_rip(cpu, env->eip);
|
||||
}
|
||||
|
||||
|
|
|
@ -126,7 +126,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
|
|||
pt->err_code |= MMU_PAGE_PT;
|
||||
}
|
||||
|
||||
uint32_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);
|
||||
uint32_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0);
|
||||
/* check protection */
|
||||
if (cr0 & CR0_WP_MASK) {
|
||||
if (pt->write_access && !pte_write_access(pte)) {
|
||||
|
@ -171,7 +171,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code,
|
|||
{
|
||||
int top_level, level;
|
||||
bool is_large = false;
|
||||
target_ulong cr3 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3);
|
||||
target_ulong cr3 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR3);
|
||||
uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
|
||||
|
||||
memset(pt, 0, sizeof(*pt));
|
||||
|
|
|
@ -61,7 +61,7 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
|
|||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
CPUX86State *env = &x86_cpu->env;
|
||||
|
||||
wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3);
|
||||
wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3);
|
||||
|
||||
env->eip = tss->eip;
|
||||
env->eflags = tss->eflags | 2;
|
||||
|
@ -110,11 +110,11 @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme
|
|||
|
||||
void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
|
||||
{
|
||||
uint64_t rip = rreg(cpu->hvf->fd, HV_X86_RIP);
|
||||
uint64_t rip = rreg(cpu->accel->fd, HV_X86_RIP);
|
||||
if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
|
||||
gate_type != VMCS_INTR_T_HWINTR &&
|
||||
gate_type != VMCS_INTR_T_NMI)) {
|
||||
int ins_len = rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH);
|
||||
int ins_len = rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH);
|
||||
macvm_set_rip(cpu, rip + ins_len);
|
||||
return;
|
||||
}
|
||||
|
@ -173,12 +173,12 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea
|
|||
//ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
|
||||
VM_PANIC("task_switch_16");
|
||||
|
||||
macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) |
|
||||
macvm_set_cr0(cpu->accel->fd, rvmcs(cpu->accel->fd, VMCS_GUEST_CR0) |
|
||||
CR0_TS_MASK);
|
||||
x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
|
||||
vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);
|
||||
|
||||
store_regs(cpu);
|
||||
|
||||
hv_vcpu_invalidate_tlb(cpu->hvf->fd);
|
||||
hv_vcpu_invalidate_tlb(cpu->accel->fd);
|
||||
}
|
||||
|
|
|
@ -32,14 +32,14 @@
|
|||
#include <Hypervisor/hv.h>
|
||||
#include <Hypervisor/hv_vmx.h>
|
||||
|
||||
void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
|
||||
void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg,
|
||||
SegmentCache *qseg, bool is_tr)
|
||||
{
|
||||
vmx_seg->sel = qseg->selector;
|
||||
vmx_seg->base = qseg->base;
|
||||
vmx_seg->limit = qseg->limit;
|
||||
|
||||
if (!qseg->selector && !x86_is_real(cpu) && !is_tr) {
|
||||
if (!qseg->selector && !x86_is_real(cs) && !is_tr) {
|
||||
/* the TR register is usable after processor reset despite
|
||||
* having a null selector */
|
||||
vmx_seg->ar = 1 << 16;
|
||||
|
@ -70,279 +70,279 @@ void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg)
|
|||
(((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT);
|
||||
}
|
||||
|
||||
void hvf_put_xsave(CPUState *cpu_state)
|
||||
void hvf_put_xsave(CPUState *cs)
|
||||
{
|
||||
void *xsave = X86_CPU(cpu_state)->env.xsave_buf;
|
||||
uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len;
|
||||
void *xsave = X86_CPU(cs)->env.xsave_buf;
|
||||
uint32_t xsave_len = X86_CPU(cs)->env.xsave_buf_len;
|
||||
|
||||
x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave, xsave_len);
|
||||
x86_cpu_xsave_all_areas(X86_CPU(cs), xsave, xsave_len);
|
||||
|
||||
if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) {
|
||||
if (hv_vcpu_write_fpstate(cs->accel->fd, xsave, xsave_len)) {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
static void hvf_put_segments(CPUState *cpu_state)
|
||||
static void hvf_put_segments(CPUState *cs)
|
||||
{
|
||||
CPUX86State *env = &X86_CPU(cpu_state)->env;
|
||||
CPUX86State *env = &X86_CPU(cs)->env;
|
||||
struct vmx_segment seg;
|
||||
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
|
||||
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
|
||||
|
||||
/* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]);
|
||||
vmx_update_tpr(cpu_state);
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer);
|
||||
/* wvmcs(cs->accel->fd, VMCS_GUEST_CR2, env->cr[2]); */
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]);
|
||||
vmx_update_tpr(cs);
|
||||
wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, env->efer);
|
||||
|
||||
macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]);
|
||||
macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]);
|
||||
macvm_set_cr4(cs->accel->fd, env->cr[4]);
|
||||
macvm_set_cr0(cs->accel->fd, env->cr[0]);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_CS);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_CS], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_CS);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_DS);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_DS], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_DS);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_ES);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_ES], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_ES);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_SS);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_SS], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_SS);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_FS);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_FS], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_FS);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_GS);
|
||||
hvf_set_segment(cs, &seg, &env->segs[R_GS], false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_GS);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->tr, true);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_TR);
|
||||
hvf_set_segment(cs, &seg, &env->tr, true);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_TR);
|
||||
|
||||
hvf_set_segment(cpu_state, &seg, &env->ldt, false);
|
||||
vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR);
|
||||
hvf_set_segment(cs, &seg, &env->ldt, false);
|
||||
vmx_write_segment_descriptor(cs, &seg, R_LDTR);
|
||||
}
|
||||
|
||||
void hvf_put_msrs(CPUState *cpu_state)
|
||||
void hvf_put_msrs(CPUState *cs)
|
||||
{
|
||||
CPUX86State *env = &X86_CPU(cpu_state)->env;
|
||||
CPUX86State *env = &X86_CPU(cs)->env;
|
||||
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS,
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS,
|
||||
env->sysenter_cs);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP,
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP,
|
||||
env->sysenter_esp);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP,
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP,
|
||||
env->sysenter_eip);
|
||||
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_STAR, env->star);
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_CSTAR, env->cstar);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_KERNELGSBASE, env->kernelgsbase);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_FMASK, env->fmask);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_LSTAR, env->lstar);
|
||||
#endif
|
||||
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base);
|
||||
hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_GSBASE, env->segs[R_GS].base);
|
||||
hv_vcpu_write_msr(cs->accel->fd, MSR_FSBASE, env->segs[R_FS].base);
|
||||
}
|
||||
|
||||
|
||||
void hvf_get_xsave(CPUState *cpu_state)
|
||||
void hvf_get_xsave(CPUState *cs)
|
||||
{
|
||||
void *xsave = X86_CPU(cpu_state)->env.xsave_buf;
|
||||
uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len;
|
||||
void *xsave = X86_CPU(cs)->env.xsave_buf;
|
||||
uint32_t xsave_len = X86_CPU(cs)->env.xsave_buf_len;
|
||||
|
||||
if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) {
|
||||
if (hv_vcpu_read_fpstate(cs->accel->fd, xsave, xsave_len)) {
|
||||
abort();
|
||||
}
|
||||
|
||||
x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave, xsave_len);
|
||||
x86_cpu_xrstor_all_areas(X86_CPU(cs), xsave, xsave_len);
|
||||
}
|
||||
|
||||
static void hvf_get_segments(CPUState *cpu_state)
|
||||
static void hvf_get_segments(CPUState *cs)
|
||||
{
|
||||
CPUX86State *env = &X86_CPU(cpu_state)->env;
|
||||
CPUX86State *env = &X86_CPU(cs)->env;
|
||||
|
||||
struct vmx_segment seg;
|
||||
|
||||
env->interrupt_injected = -1;
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_CS);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_CS);
|
||||
hvf_get_segment(&env->segs[R_CS], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_DS);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_DS);
|
||||
hvf_get_segment(&env->segs[R_DS], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_ES);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_ES);
|
||||
hvf_get_segment(&env->segs[R_ES], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_FS);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_FS);
|
||||
hvf_get_segment(&env->segs[R_FS], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_GS);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_GS);
|
||||
hvf_get_segment(&env->segs[R_GS], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_SS);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_SS);
|
||||
hvf_get_segment(&env->segs[R_SS], &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_TR);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_TR);
|
||||
hvf_get_segment(&env->tr, &seg);
|
||||
|
||||
vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR);
|
||||
vmx_read_segment_descriptor(cs, &seg, R_LDTR);
|
||||
hvf_get_segment(&env->ldt, &seg);
|
||||
|
||||
env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT);
|
||||
env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE);
|
||||
env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE);
|
||||
env->idt.limit = rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT);
|
||||
env->idt.base = rvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE);
|
||||
env->gdt.limit = rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT);
|
||||
env->gdt.base = rvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE);
|
||||
|
||||
env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0);
|
||||
env->cr[0] = rvmcs(cs->accel->fd, VMCS_GUEST_CR0);
|
||||
env->cr[2] = 0;
|
||||
env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3);
|
||||
env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4);
|
||||
env->cr[3] = rvmcs(cs->accel->fd, VMCS_GUEST_CR3);
|
||||
env->cr[4] = rvmcs(cs->accel->fd, VMCS_GUEST_CR4);
|
||||
|
||||
env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER);
|
||||
env->efer = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER);
|
||||
}
|
||||
|
||||
void hvf_get_msrs(CPUState *cpu_state)
|
||||
void hvf_get_msrs(CPUState *cs)
|
||||
{
|
||||
CPUX86State *env = &X86_CPU(cpu_state)->env;
|
||||
CPUX86State *env = &X86_CPU(cs)->env;
|
||||
uint64_t tmp;
|
||||
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_CS, &tmp);
|
||||
env->sysenter_cs = tmp;
|
||||
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_ESP, &tmp);
|
||||
env->sysenter_esp = tmp;
|
||||
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_SYSENTER_EIP, &tmp);
|
||||
env->sysenter_eip = tmp;
|
||||
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_STAR, &env->star);
|
||||
|
||||
#ifdef TARGET_X86_64
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar);
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase);
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask);
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_CSTAR, &env->cstar);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_KERNELGSBASE, &env->kernelgsbase);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_FMASK, &env->fmask);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_LSTAR, &env->lstar);
|
||||
#endif
|
||||
|
||||
hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp);
|
||||
hv_vcpu_read_msr(cs->accel->fd, MSR_IA32_APICBASE, &tmp);
|
||||
|
||||
env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET);
|
||||
env->tsc = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET);
|
||||
}
|
||||
|
||||
int hvf_put_registers(CPUState *cpu_state)
|
||||
int hvf_put_registers(CPUState *cs)
|
||||
{
|
||||
X86CPU *x86cpu = X86_CPU(cpu_state);
|
||||
X86CPU *x86cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &x86cpu->env;
|
||||
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip);
|
||||
wreg(cs->accel->fd, HV_X86_RAX, env->regs[R_EAX]);
|
||||
wreg(cs->accel->fd, HV_X86_RBX, env->regs[R_EBX]);
|
||||
wreg(cs->accel->fd, HV_X86_RCX, env->regs[R_ECX]);
|
||||
wreg(cs->accel->fd, HV_X86_RDX, env->regs[R_EDX]);
|
||||
wreg(cs->accel->fd, HV_X86_RBP, env->regs[R_EBP]);
|
||||
wreg(cs->accel->fd, HV_X86_RSP, env->regs[R_ESP]);
|
||||
wreg(cs->accel->fd, HV_X86_RSI, env->regs[R_ESI]);
|
||||
wreg(cs->accel->fd, HV_X86_RDI, env->regs[R_EDI]);
|
||||
wreg(cs->accel->fd, HV_X86_R8, env->regs[8]);
|
||||
wreg(cs->accel->fd, HV_X86_R9, env->regs[9]);
|
||||
wreg(cs->accel->fd, HV_X86_R10, env->regs[10]);
|
||||
wreg(cs->accel->fd, HV_X86_R11, env->regs[11]);
|
||||
wreg(cs->accel->fd, HV_X86_R12, env->regs[12]);
|
||||
wreg(cs->accel->fd, HV_X86_R13, env->regs[13]);
|
||||
wreg(cs->accel->fd, HV_X86_R14, env->regs[14]);
|
||||
wreg(cs->accel->fd, HV_X86_R15, env->regs[15]);
|
||||
wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
|
||||
wreg(cs->accel->fd, HV_X86_RIP, env->eip);
|
||||
|
||||
wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0);
|
||||
wreg(cs->accel->fd, HV_X86_XCR0, env->xcr0);
|
||||
|
||||
hvf_put_xsave(cpu_state);
|
||||
hvf_put_xsave(cs);
|
||||
|
||||
hvf_put_segments(cpu_state);
|
||||
hvf_put_segments(cs);
|
||||
|
||||
hvf_put_msrs(cpu_state);
|
||||
hvf_put_msrs(cs);
|
||||
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]);
|
||||
wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]);
|
||||
wreg(cs->accel->fd, HV_X86_DR0, env->dr[0]);
|
||||
wreg(cs->accel->fd, HV_X86_DR1, env->dr[1]);
|
||||
wreg(cs->accel->fd, HV_X86_DR2, env->dr[2]);
|
||||
wreg(cs->accel->fd, HV_X86_DR3, env->dr[3]);
|
||||
wreg(cs->accel->fd, HV_X86_DR4, env->dr[4]);
|
||||
wreg(cs->accel->fd, HV_X86_DR5, env->dr[5]);
|
||||
wreg(cs->accel->fd, HV_X86_DR6, env->dr[6]);
|
||||
wreg(cs->accel->fd, HV_X86_DR7, env->dr[7]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hvf_get_registers(CPUState *cpu_state)
|
||||
int hvf_get_registers(CPUState *cs)
|
||||
{
|
||||
X86CPU *x86cpu = X86_CPU(cpu_state);
|
||||
X86CPU *x86cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &x86cpu->env;
|
||||
|
||||
env->regs[R_EAX] = rreg(cpu_state->hvf->fd, HV_X86_RAX);
|
||||
env->regs[R_EBX] = rreg(cpu_state->hvf->fd, HV_X86_RBX);
|
||||
env->regs[R_ECX] = rreg(cpu_state->hvf->fd, HV_X86_RCX);
|
||||
env->regs[R_EDX] = rreg(cpu_state->hvf->fd, HV_X86_RDX);
|
||||
env->regs[R_EBP] = rreg(cpu_state->hvf->fd, HV_X86_RBP);
|
||||
env->regs[R_ESP] = rreg(cpu_state->hvf->fd, HV_X86_RSP);
|
||||
env->regs[R_ESI] = rreg(cpu_state->hvf->fd, HV_X86_RSI);
|
||||
env->regs[R_EDI] = rreg(cpu_state->hvf->fd, HV_X86_RDI);
|
||||
env->regs[8] = rreg(cpu_state->hvf->fd, HV_X86_R8);
|
||||
env->regs[9] = rreg(cpu_state->hvf->fd, HV_X86_R9);
|
||||
env->regs[10] = rreg(cpu_state->hvf->fd, HV_X86_R10);
|
||||
env->regs[11] = rreg(cpu_state->hvf->fd, HV_X86_R11);
|
||||
env->regs[12] = rreg(cpu_state->hvf->fd, HV_X86_R12);
|
||||
env->regs[13] = rreg(cpu_state->hvf->fd, HV_X86_R13);
|
||||
env->regs[14] = rreg(cpu_state->hvf->fd, HV_X86_R14);
|
||||
env->regs[15] = rreg(cpu_state->hvf->fd, HV_X86_R15);
|
||||
env->regs[R_EAX] = rreg(cs->accel->fd, HV_X86_RAX);
|
||||
env->regs[R_EBX] = rreg(cs->accel->fd, HV_X86_RBX);
|
||||
env->regs[R_ECX] = rreg(cs->accel->fd, HV_X86_RCX);
|
||||
env->regs[R_EDX] = rreg(cs->accel->fd, HV_X86_RDX);
|
||||
env->regs[R_EBP] = rreg(cs->accel->fd, HV_X86_RBP);
|
||||
env->regs[R_ESP] = rreg(cs->accel->fd, HV_X86_RSP);
|
||||
env->regs[R_ESI] = rreg(cs->accel->fd, HV_X86_RSI);
|
||||
env->regs[R_EDI] = rreg(cs->accel->fd, HV_X86_RDI);
|
||||
env->regs[8] = rreg(cs->accel->fd, HV_X86_R8);
|
||||
env->regs[9] = rreg(cs->accel->fd, HV_X86_R9);
|
||||
env->regs[10] = rreg(cs->accel->fd, HV_X86_R10);
|
||||
env->regs[11] = rreg(cs->accel->fd, HV_X86_R11);
|
||||
env->regs[12] = rreg(cs->accel->fd, HV_X86_R12);
|
||||
env->regs[13] = rreg(cs->accel->fd, HV_X86_R13);
|
||||
env->regs[14] = rreg(cs->accel->fd, HV_X86_R14);
|
||||
env->regs[15] = rreg(cs->accel->fd, HV_X86_R15);
|
||||
|
||||
env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
|
||||
env->eip = rreg(cpu_state->hvf->fd, HV_X86_RIP);
|
||||
env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
|
||||
env->eip = rreg(cs->accel->fd, HV_X86_RIP);
|
||||
|
||||
hvf_get_xsave(cpu_state);
|
||||
env->xcr0 = rreg(cpu_state->hvf->fd, HV_X86_XCR0);
|
||||
hvf_get_xsave(cs);
|
||||
env->xcr0 = rreg(cs->accel->fd, HV_X86_XCR0);
|
||||
|
||||
hvf_get_segments(cpu_state);
|
||||
hvf_get_msrs(cpu_state);
|
||||
hvf_get_segments(cs);
|
||||
hvf_get_msrs(cs);
|
||||
|
||||
env->dr[0] = rreg(cpu_state->hvf->fd, HV_X86_DR0);
|
||||
env->dr[1] = rreg(cpu_state->hvf->fd, HV_X86_DR1);
|
||||
env->dr[2] = rreg(cpu_state->hvf->fd, HV_X86_DR2);
|
||||
env->dr[3] = rreg(cpu_state->hvf->fd, HV_X86_DR3);
|
||||
env->dr[4] = rreg(cpu_state->hvf->fd, HV_X86_DR4);
|
||||
env->dr[5] = rreg(cpu_state->hvf->fd, HV_X86_DR5);
|
||||
env->dr[6] = rreg(cpu_state->hvf->fd, HV_X86_DR6);
|
||||
env->dr[7] = rreg(cpu_state->hvf->fd, HV_X86_DR7);
|
||||
env->dr[0] = rreg(cs->accel->fd, HV_X86_DR0);
|
||||
env->dr[1] = rreg(cs->accel->fd, HV_X86_DR1);
|
||||
env->dr[2] = rreg(cs->accel->fd, HV_X86_DR2);
|
||||
env->dr[3] = rreg(cs->accel->fd, HV_X86_DR3);
|
||||
env->dr[4] = rreg(cs->accel->fd, HV_X86_DR4);
|
||||
env->dr[5] = rreg(cs->accel->fd, HV_X86_DR5);
|
||||
env->dr[6] = rreg(cs->accel->fd, HV_X86_DR6);
|
||||
env->dr[7] = rreg(cs->accel->fd, HV_X86_DR7);
|
||||
|
||||
x86_update_hflags(env);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vmx_set_int_window_exiting(CPUState *cpu)
|
||||
static void vmx_set_int_window_exiting(CPUState *cs)
|
||||
{
|
||||
uint64_t val;
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |
|
||||
val = rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val |
|
||||
VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
|
||||
}
|
||||
|
||||
void vmx_clear_int_window_exiting(CPUState *cpu)
|
||||
void vmx_clear_int_window_exiting(CPUState *cs)
|
||||
{
|
||||
uint64_t val;
|
||||
val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &
|
||||
val = rvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS);
|
||||
wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val &
|
||||
~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
|
||||
}
|
||||
|
||||
bool hvf_inject_interrupts(CPUState *cpu_state)
|
||||
bool hvf_inject_interrupts(CPUState *cs)
|
||||
{
|
||||
X86CPU *x86cpu = X86_CPU(cpu_state);
|
||||
X86CPU *x86cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &x86cpu->env;
|
||||
|
||||
uint8_t vector;
|
||||
|
@ -372,89 +372,89 @@ bool hvf_inject_interrupts(CPUState *cpu_state)
|
|||
uint64_t info = 0;
|
||||
if (have_event) {
|
||||
info = vector | intr_type | VMCS_INTR_VALID;
|
||||
uint64_t reason = rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON);
|
||||
uint64_t reason = rvmcs(cs->accel->fd, VMCS_EXIT_REASON);
|
||||
if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) {
|
||||
vmx_clear_nmi_blocking(cpu_state);
|
||||
vmx_clear_nmi_blocking(cs);
|
||||
}
|
||||
|
||||
if (!(env->hflags2 & HF2_NMI_MASK) || intr_type != VMCS_INTR_T_NMI) {
|
||||
info &= ~(1 << 12); /* clear undefined bit */
|
||||
if (intr_type == VMCS_INTR_T_SWINTR ||
|
||||
intr_type == VMCS_INTR_T_SWEXCEPTION) {
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);
|
||||
wvmcs(cs->accel->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);
|
||||
}
|
||||
|
||||
if (env->has_error_code) {
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR,
|
||||
wvmcs(cs->accel->fd, VMCS_ENTRY_EXCEPTION_ERROR,
|
||||
env->error_code);
|
||||
/* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */
|
||||
info |= VMCS_INTR_DEL_ERRCODE;
|
||||
}
|
||||
/*printf("reinject %lx err %d\n", info, err);*/
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
|
||||
wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info);
|
||||
};
|
||||
}
|
||||
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_NMI) {
|
||||
if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) {
|
||||
cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
|
||||
info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI;
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
|
||||
wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info);
|
||||
} else {
|
||||
vmx_set_nmi_window_exiting(cpu_state);
|
||||
vmx_set_nmi_window_exiting(cs);
|
||||
}
|
||||
}
|
||||
|
||||
if (!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
|
||||
(cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
|
||||
(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
||||
(env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) {
|
||||
int line = cpu_get_pic_interrupt(&x86cpu->env);
|
||||
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
||||
if (line >= 0) {
|
||||
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line |
|
||||
wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line |
|
||||
VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
|
||||
}
|
||||
}
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
vmx_set_int_window_exiting(cpu_state);
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
vmx_set_int_window_exiting(cs);
|
||||
}
|
||||
return (cpu_state->interrupt_request
|
||||
return (cs->interrupt_request
|
||||
& (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR));
|
||||
}
|
||||
|
||||
int hvf_process_events(CPUState *cpu_state)
|
||||
int hvf_process_events(CPUState *cs)
|
||||
{
|
||||
X86CPU *cpu = X86_CPU(cpu_state);
|
||||
X86CPU *cpu = X86_CPU(cs);
|
||||
CPUX86State *env = &cpu->env;
|
||||
|
||||
if (!cpu_state->vcpu_dirty) {
|
||||
if (!cs->vcpu_dirty) {
|
||||
/* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */
|
||||
env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
|
||||
env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
|
||||
}
|
||||
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
|
||||
cpu_synchronize_state(cpu_state);
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
|
||||
cpu_synchronize_state(cs);
|
||||
do_cpu_init(cpu);
|
||||
}
|
||||
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) {
|
||||
cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL;
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
|
||||
apic_poll_irq(cpu->apic_state);
|
||||
}
|
||||
if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
|
||||
if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
||||
(env->eflags & IF_MASK)) ||
|
||||
(cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
|
||||
cpu_state->halted = 0;
|
||||
(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
|
||||
cs->halted = 0;
|
||||
}
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) {
|
||||
cpu_synchronize_state(cpu_state);
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
|
||||
cpu_synchronize_state(cs);
|
||||
do_cpu_sipi(cpu);
|
||||
}
|
||||
if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) {
|
||||
cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR;
|
||||
cpu_synchronize_state(cpu_state);
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
|
||||
cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
|
||||
cpu_synchronize_state(cs);
|
||||
apic_handle_tpr_access_report(cpu->apic_state, env->eip,
|
||||
env->tpr_access_type);
|
||||
}
|
||||
return cpu_state->halted;
|
||||
return cs->halted;
|
||||
}
|
||||
|
|
|
@ -20,15 +20,15 @@
|
|||
#include "cpu.h"
|
||||
#include "x86_descr.h"
|
||||
|
||||
int hvf_process_events(CPUState *);
|
||||
bool hvf_inject_interrupts(CPUState *);
|
||||
void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
|
||||
int hvf_process_events(CPUState *cs);
|
||||
bool hvf_inject_interrupts(CPUState *cs);
|
||||
void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg,
|
||||
SegmentCache *qseg, bool is_tr);
|
||||
void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg);
|
||||
void hvf_put_xsave(CPUState *cpu_state);
|
||||
void hvf_put_msrs(CPUState *cpu_state);
|
||||
void hvf_get_xsave(CPUState *cpu_state);
|
||||
void hvf_get_msrs(CPUState *cpu_state);
|
||||
void vmx_clear_int_window_exiting(CPUState *cpu);
|
||||
void vmx_update_tpr(CPUState *cpu);
|
||||
void hvf_put_xsave(CPUState *cs);
|
||||
void hvf_put_msrs(CPUState *cs);
|
||||
void hvf_get_xsave(CPUState *cs);
|
||||
void hvf_get_msrs(CPUState *cs);
|
||||
void vmx_clear_int_window_exiting(CPUState *cs);
|
||||
void vmx_update_tpr(CPUState *cs);
|
||||
#endif
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
|
||||
#include <nvmm.h>
|
||||
|
||||
struct qemu_vcpu {
|
||||
struct AccelCPUState {
|
||||
struct nvmm_vcpu vcpu;
|
||||
uint8_t tpr;
|
||||
bool stop;
|
||||
|
@ -49,12 +49,6 @@ struct qemu_machine {
|
|||
static bool nvmm_allowed;
|
||||
static struct qemu_machine qemu_mach;
|
||||
|
||||
static struct qemu_vcpu *
|
||||
get_qemu_vcpu(CPUState *cpu)
|
||||
{
|
||||
return (struct qemu_vcpu *)cpu->hax_vcpu;
|
||||
}
|
||||
|
||||
static struct nvmm_machine *
|
||||
get_nvmm_mach(void)
|
||||
{
|
||||
|
@ -86,7 +80,7 @@ nvmm_set_registers(CPUState *cpu)
|
|||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
struct nvmm_x64_state *state = vcpu->state;
|
||||
uint64_t bitmap;
|
||||
|
@ -223,7 +217,7 @@ nvmm_get_registers(CPUState *cpu)
|
|||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct nvmm_x64_state *state = vcpu->state;
|
||||
|
@ -347,7 +341,7 @@ static bool
|
|||
nvmm_can_take_int(CPUState *cpu)
|
||||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
|
||||
|
@ -372,7 +366,7 @@ nvmm_can_take_int(CPUState *cpu)
|
|||
static bool
|
||||
nvmm_can_take_nmi(CPUState *cpu)
|
||||
{
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
|
||||
/*
|
||||
* Contrary to INTs, NMIs always schedule an exit when they are
|
||||
|
@ -395,7 +389,7 @@ nvmm_vcpu_pre_run(CPUState *cpu)
|
|||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct nvmm_x64_state *state = vcpu->state;
|
||||
|
@ -478,7 +472,7 @@ nvmm_vcpu_pre_run(CPUState *cpu)
|
|||
static void
|
||||
nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit)
|
||||
{
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
uint64_t tpr;
|
||||
|
@ -565,7 +559,7 @@ static int
|
|||
nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu,
|
||||
struct nvmm_vcpu_exit *exit)
|
||||
{
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct nvmm_x64_state *state = vcpu->state;
|
||||
|
@ -610,7 +604,7 @@ static int
|
|||
nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu,
|
||||
struct nvmm_vcpu_exit *exit)
|
||||
{
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct nvmm_x64_state *state = vcpu->state;
|
||||
|
@ -686,7 +680,7 @@ nvmm_vcpu_loop(CPUState *cpu)
|
|||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct nvmm_vcpu_exit *exit = vcpu->exit;
|
||||
|
@ -892,7 +886,7 @@ static void
|
|||
nvmm_ipi_signal(int sigcpu)
|
||||
{
|
||||
if (current_cpu) {
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(current_cpu);
|
||||
AccelCPUState *qcpu = current_cpu->accel;
|
||||
#if NVMM_USER_VERSION >= 2
|
||||
struct nvmm_vcpu *vcpu = &qcpu->vcpu;
|
||||
nvmm_vcpu_stop(vcpu);
|
||||
|
@ -926,7 +920,7 @@ nvmm_init_vcpu(CPUState *cpu)
|
|||
struct nvmm_vcpu_conf_cpuid cpuid;
|
||||
struct nvmm_vcpu_conf_tpr tpr;
|
||||
Error *local_error = NULL;
|
||||
struct qemu_vcpu *qcpu;
|
||||
AccelCPUState *qcpu;
|
||||
int ret, err;
|
||||
|
||||
nvmm_init_cpu_signals();
|
||||
|
@ -942,11 +936,7 @@ nvmm_init_vcpu(CPUState *cpu)
|
|||
}
|
||||
}
|
||||
|
||||
qcpu = g_malloc0(sizeof(*qcpu));
|
||||
if (qcpu == NULL) {
|
||||
error_report("NVMM: Failed to allocate VCPU context.");
|
||||
return -ENOMEM;
|
||||
}
|
||||
qcpu = g_new0(AccelCPUState, 1);
|
||||
|
||||
ret = nvmm_vcpu_create(mach, cpu->cpu_index, &qcpu->vcpu);
|
||||
if (ret == -1) {
|
||||
|
@ -995,7 +985,7 @@ nvmm_init_vcpu(CPUState *cpu)
|
|||
}
|
||||
|
||||
cpu->vcpu_dirty = true;
|
||||
cpu->hax_vcpu = (struct hax_vcpu_state *)qcpu;
|
||||
cpu->accel = qcpu;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1027,10 +1017,10 @@ void
|
|||
nvmm_destroy_vcpu(CPUState *cpu)
|
||||
{
|
||||
struct nvmm_machine *mach = get_nvmm_mach();
|
||||
struct qemu_vcpu *qcpu = get_qemu_vcpu(cpu);
|
||||
AccelCPUState *qcpu = cpu->accel;
|
||||
|
||||
nvmm_vcpu_destroy(mach, &qcpu->vcpu);
|
||||
g_free(cpu->hax_vcpu);
|
||||
g_free(cpu->accel);
|
||||
}
|
||||
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
@ -1138,7 +1128,7 @@ static MemoryListener nvmm_memory_listener = {
|
|||
.region_add = nvmm_region_add,
|
||||
.region_del = nvmm_region_del,
|
||||
.log_sync = nvmm_log_sync,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
static void
|
||||
|
|
|
@ -71,9 +71,6 @@ static void whpx_start_vcpu_thread(CPUState *cpu)
|
|||
cpu->cpu_index);
|
||||
qemu_thread_create(cpu->thread, thread_name, whpx_cpu_thread_fn,
|
||||
cpu, QEMU_THREAD_JOINABLE);
|
||||
#ifdef _WIN32
|
||||
cpu->hThread = qemu_thread_get_handle(cpu->thread);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void whpx_kick_vcpu_thread(CPUState *cpu)
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
#include "whpx-internal.h"
|
||||
#include "whpx-accel-ops.h"
|
||||
|
||||
#include <WinHvPlatform.h>
|
||||
#include <WinHvEmulation.h>
|
||||
#include <winhvplatform.h>
|
||||
#include <winhvemulation.h>
|
||||
|
||||
#define HYPERV_APIC_BUS_FREQUENCY (200000000ULL)
|
||||
|
||||
|
@ -229,7 +229,7 @@ typedef enum WhpxStepMode {
|
|||
WHPX_STEP_EXCLUSIVE,
|
||||
} WhpxStepMode;
|
||||
|
||||
struct whpx_vcpu {
|
||||
struct AccelCPUState {
|
||||
WHV_EMULATOR_HANDLE emulator;
|
||||
bool window_registered;
|
||||
bool interruptable;
|
||||
|
@ -256,15 +256,6 @@ static bool whpx_has_xsave(void)
|
|||
return whpx_xsave_cap.XsaveSupport;
|
||||
}
|
||||
|
||||
/*
|
||||
* VP support
|
||||
*/
|
||||
|
||||
static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu)
|
||||
{
|
||||
return (struct whpx_vcpu *)cpu->hax_vcpu;
|
||||
}
|
||||
|
||||
static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v86,
|
||||
int r86)
|
||||
{
|
||||
|
@ -390,7 +381,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)
|
|||
static void whpx_set_registers(CPUState *cpu, int level)
|
||||
{
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct whpx_register_set vcxt;
|
||||
|
@ -609,7 +600,7 @@ static void whpx_get_xcrs(CPUState *cpu)
|
|||
static void whpx_get_registers(CPUState *cpu)
|
||||
{
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct whpx_register_set vcxt;
|
||||
|
@ -892,7 +883,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = {
|
|||
static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)
|
||||
{
|
||||
HRESULT hr;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
WHV_EMULATOR_STATUS emu_status;
|
||||
|
||||
hr = whp_dispatch.WHvEmulatorTryMmioEmulation(
|
||||
|
@ -917,7 +908,7 @@ static int whpx_handle_portio(CPUState *cpu,
|
|||
WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx)
|
||||
{
|
||||
HRESULT hr;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
WHV_EMULATOR_STATUS emu_status;
|
||||
|
||||
hr = whp_dispatch.WHvEmulatorTryIoEmulation(
|
||||
|
@ -1417,7 +1408,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid)
|
|||
* of QEMU, nor this port by calling WHvSetVirtualProcessorRegisters().
|
||||
* This is the most common case.
|
||||
*/
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
return vcpu->exit_ctx.VpContext.Rip;
|
||||
} else {
|
||||
/*
|
||||
|
@ -1468,7 +1459,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
|
|||
{
|
||||
HRESULT hr;
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
int irq;
|
||||
|
@ -1590,7 +1581,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)
|
|||
|
||||
static void whpx_vcpu_post_run(CPUState *cpu)
|
||||
{
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
|
||||
|
@ -1617,7 +1608,7 @@ static void whpx_vcpu_process_async_events(CPUState *cpu)
|
|||
{
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
|
||||
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
|
||||
!(env->hflags & HF_SMM_MASK)) {
|
||||
|
@ -1656,7 +1647,7 @@ static int whpx_vcpu_run(CPUState *cpu)
|
|||
{
|
||||
HRESULT hr;
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
struct whpx_breakpoint *stepped_over_bp = NULL;
|
||||
WhpxStepMode exclusive_step_mode = WHPX_STEP_NONE;
|
||||
int ret;
|
||||
|
@ -2154,7 +2145,7 @@ int whpx_init_vcpu(CPUState *cpu)
|
|||
{
|
||||
HRESULT hr;
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = NULL;
|
||||
AccelCPUState *vcpu = NULL;
|
||||
Error *local_error = NULL;
|
||||
CPUX86State *env = cpu->env_ptr;
|
||||
X86CPU *x86_cpu = X86_CPU(cpu);
|
||||
|
@ -2177,13 +2168,7 @@ int whpx_init_vcpu(CPUState *cpu)
|
|||
}
|
||||
}
|
||||
|
||||
vcpu = g_new0(struct whpx_vcpu, 1);
|
||||
|
||||
if (!vcpu) {
|
||||
error_report("WHPX: Failed to allocte VCPU context.");
|
||||
ret = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
vcpu = g_new0(AccelCPUState, 1);
|
||||
|
||||
hr = whp_dispatch.WHvEmulatorCreateEmulator(
|
||||
&whpx_emu_callbacks,
|
||||
|
@ -2258,7 +2243,7 @@ int whpx_init_vcpu(CPUState *cpu)
|
|||
|
||||
vcpu->interruptable = true;
|
||||
cpu->vcpu_dirty = true;
|
||||
cpu->hax_vcpu = (struct hax_vcpu_state *)vcpu;
|
||||
cpu->accel = vcpu;
|
||||
max_vcpu_index = max(max_vcpu_index, cpu->cpu_index);
|
||||
qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr);
|
||||
|
||||
|
@ -2296,11 +2281,11 @@ int whpx_vcpu_exec(CPUState *cpu)
|
|||
void whpx_destroy_vcpu(CPUState *cpu)
|
||||
{
|
||||
struct whpx_state *whpx = &whpx_global;
|
||||
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
|
||||
AccelCPUState *vcpu = cpu->accel;
|
||||
|
||||
whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index);
|
||||
whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator);
|
||||
g_free(cpu->hax_vcpu);
|
||||
g_free(cpu->accel);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -2427,7 +2412,7 @@ static MemoryListener whpx_memory_listener = {
|
|||
.region_add = whpx_region_add,
|
||||
.region_del = whpx_region_del,
|
||||
.log_sync = whpx_log_sync,
|
||||
.priority = 10,
|
||||
.priority = MEMORY_LISTENER_PRIORITY_ACCEL,
|
||||
};
|
||||
|
||||
static void whpx_memory_init(void)
|
||||
|
@ -2613,8 +2598,8 @@ static int whpx_accel_init(MachineState *ms)
|
|||
sizeof(WHV_PARTITION_PROPERTY));
|
||||
|
||||
if (FAILED(hr)) {
|
||||
error_report("WHPX: Failed to set partition core count to %d,"
|
||||
" hr=%08lx", ms->smp.cores, hr);
|
||||
error_report("WHPX: Failed to set partition processor count to %u,"
|
||||
" hr=%08lx", prop.ProcessorCount, hr);
|
||||
ret = -EINVAL;
|
||||
goto error;
|
||||
}
|
||||
|
|
|
@ -2,8 +2,8 @@
|
|||
#define TARGET_I386_WHPX_INTERNAL_H
|
||||
|
||||
#include <windows.h>
|
||||
#include <WinHvPlatform.h>
|
||||
#include <WinHvEmulation.h>
|
||||
#include <winhvplatform.h>
|
||||
#include <winhvemulation.h>
|
||||
|
||||
typedef enum WhpxBreakpointState {
|
||||
WHPX_BP_CLEARED = 0,
|
||||
|
|
|
@ -1149,8 +1149,10 @@ struct CPUArchState {
|
|||
int nb_pids; /* Number of available PID registers */
|
||||
int tlb_type; /* Type of TLB we're dealing with */
|
||||
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
|
||||
#ifdef CONFIG_KVM
|
||||
bool tlb_dirty; /* Set to non-zero when modifying TLB */
|
||||
bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
|
||||
#endif /* CONFIG_KVM */
|
||||
uint32_t tlb_need_flush; /* Delayed flush needed */
|
||||
#define TLB_NEED_LOCAL_FLUSH 0x1
|
||||
#define TLB_NEED_GLOBAL_FLUSH 0x2
|
||||
|
|
|
@ -930,10 +930,12 @@ static void mmubooke_dump_mmu(CPUPPCState *env)
|
|||
ppcemb_tlb_t *entry;
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
||||
qemu_printf("Cannot access KVM TLB\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
qemu_printf("\nTLB:\n");
|
||||
qemu_printf("Effective Physical Size PID Prot "
|
||||
|
@ -1021,10 +1023,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env)
|
|||
int offset = 0;
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
if (kvm_enabled() && !env->kvm_sw_tlb) {
|
||||
qemu_printf("Cannot access KVM TLB\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
|
||||
int size = booke206_tlb_size(env, i);
|
||||
|
|
|
@ -584,7 +584,7 @@ static void riscv_host_cpu_init(Object *obj)
|
|||
#endif
|
||||
riscv_cpu_add_user_properties(obj);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_KVM */
|
||||
|
||||
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
|
||||
{
|
||||
|
|
|
@ -363,12 +363,14 @@ struct CPUArchState {
|
|||
hwaddr kernel_addr;
|
||||
hwaddr fdt_addr;
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
/* kvm timer */
|
||||
bool kvm_timer_dirty;
|
||||
uint64_t kvm_timer_time;
|
||||
uint64_t kvm_timer_compare;
|
||||
uint64_t kvm_timer_state;
|
||||
uint64_t kvm_timer_frequency;
|
||||
#endif /* CONFIG_KVM */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -194,12 +194,13 @@ static const VMStateDescription vmstate_rv128 = {
|
|||
}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_KVM
|
||||
static bool kvmtimer_needed(void *opaque)
|
||||
{
|
||||
return kvm_enabled();
|
||||
}
|
||||
|
||||
static int cpu_post_load(void *opaque, int version_id)
|
||||
static int cpu_kvmtimer_post_load(void *opaque, int version_id)
|
||||
{
|
||||
RISCVCPU *cpu = opaque;
|
||||
CPURISCVState *env = &cpu->env;
|
||||
|
@ -213,7 +214,7 @@ static const VMStateDescription vmstate_kvmtimer = {
|
|||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.needed = kvmtimer_needed,
|
||||
.post_load = cpu_post_load,
|
||||
.post_load = cpu_kvmtimer_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
|
||||
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
|
||||
|
@ -221,6 +222,7 @@ static const VMStateDescription vmstate_kvmtimer = {
|
|||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
static bool debug_needed(void *opaque)
|
||||
{
|
||||
|
@ -409,7 +411,9 @@ const VMStateDescription vmstate_riscv_cpu = {
|
|||
&vmstate_vector,
|
||||
&vmstate_pointermasking,
|
||||
&vmstate_rv128,
|
||||
#ifdef CONFIG_KVM
|
||||
&vmstate_kvmtimer,
|
||||
#endif
|
||||
&vmstate_envcfg,
|
||||
&vmstate_debug,
|
||||
&vmstate_smstateen,
|
||||
|
|
Loading…
Reference in New Issue