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xemu/target/riscv/insn_trans/trans_rvb.c.inc

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target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:03 +00:00
/*
* RISC-V translation routines for the RVB Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_clz);
}
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctz);
}
target/riscv: rvb: count bits set Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:04 +00:00
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
}
target/riscv: rvb: logic-with-negate Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:05 +00:00
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, tcg_gen_eqv_tl);
}
target/riscv: rvb: pack two words into one register Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:06 +00:00
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_pack);
}
static bool trans_packu(DisasContext *ctx, arg_packu *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packu);
}
static bool trans_packh(DisasContext *ctx, arg_packh *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packh);
}
target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:03 +00:00
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_clzw);
}
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctzw);
}
target/riscv: rvb: count bits set Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:04 +00:00
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
}
target/riscv: rvb: pack two words into one register Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 16:06:06 +00:00
static bool trans_packw(DisasContext *ctx, arg_packw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packw);
}
static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_arith(ctx, a, gen_packuw);
}