xemu/target/mips/tcg/octeon.decode

# Octeon Architecture Module instruction set
#
# Copyright (C) 2022 Pavel Dovgalyuk
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#

# Branch on bit set or clear
# BBIT0      110010 ..... ..... ................
# BBIT032    110110 ..... ..... ................
# BBIT1      111010 ..... ..... ................
# BBIT132    111110 ..... ..... ................

%bbit_p      28:1 16:5
BBIT         11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
target/mips: introduce decodetree structure for Cavium Octeon extension This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> 2022-06-20 12:05:21 +00:00			`# Octeon Architecture Module instruction set`
			`#`
			`# Copyright (C) 2022 Pavel Dovgalyuk`
			`#`
			`# SPDX-License-Identifier: LGPL-2.1-or-later`
			`#`
target/mips: implement Octeon-specific BBIT instructions This patch introduces Octeon-specific decoder and implements check-bit-and-jump instructions. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> 2022-06-20 12:05:27 +00:00
			`# Branch on bit set or clear`
			`# BBIT0 110010 ..... ..... ................`
			`# BBIT032 110110 ..... ..... ................`
			`# BBIT1 111010 ..... ..... ................`
			`# BBIT132 111110 ..... ..... ................`

			`%bbit_p 28:1 16:5`
			`BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p`