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xemu/target/riscv/insn_trans/trans_rvv.inc.c

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target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:52 +00:00
/*
* RISC-V translation routines for the RVV Standard Extension.
*
* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:54 +00:00
#include "tcg/tcg-op-gvec.h"
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:52 +00:00
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
if (!has_ext(ctx, RVV)) {
return false;
}
s2 = tcg_temp_new();
dst = tcg_temp_new();
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
s1 = tcg_temp_new();
gen_get_gpr(s1, a->rs1);
}
gen_get_gpr(s2, a->rs2);
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
lookup_and_goto_ptr(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
return true;
}
static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
{
TCGv s1, s2, dst;
if (!has_ext(ctx, RVV)) {
return false;
}
s2 = tcg_const_tl(a->zimm);
dst = tcg_temp_new();
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
s1 = tcg_temp_new();
gen_get_gpr(s1, a->rs1);
}
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst);
return true;
}
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:54 +00:00
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{
return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
}
/* check functions */
/*
* In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
* So RVV is also be checked in this function.
*/
static bool vext_check_isa_ill(DisasContext *s)
{
return !s->vill;
}
/*
* There are two rules check here.
*
* 1. Vector register numbers are multiples of LMUL. (Section 3.2)
*
* 2. For all widening instructions, the destination LMUL value must also be
* a supported LMUL value. (Section 11.2)
*/
static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
{
/*
* The destination vector register group results are arranged as if both
* SEW and LMUL were at twice their current settings. (Section 11.2).
*/
int legal = widen ? 2 << s->lmul : 1 << s->lmul;
return !((s->lmul == 0x3 && widen) || (reg % legal));
}
/*
* There are two rules check here.
*
* 1. The destination vector register group for a masked vector instruction can
* only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
*
* 2. In widen instructions and some other insturctions, like vslideup.vx,
* there is no need to check whether LMUL=1.
*/
static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
bool force)
{
return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
}
/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
static bool vext_check_nf(DisasContext *s, uint32_t nf)
{
return (1 << s->lmul) * nf <= 8;
}
/* common translation macro */
#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
{ \
if (CHECK(s, a)) { \
return OP(s, a, SEQ); \
} \
return false; \
}
/*
*** unit stride load and store
*/
typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
TCGv_env, TCGv_i32);
static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
gen_helper_ldst_us *fn, DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base;
TCGv_i32 desc;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = tcg_temp_new();
/*
* As simd_desc supports at most 256 bytes, and in this implementation,
* the max vector group length is 2048 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
*/
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
fn(dest, mask, base, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over);
return true;
}
static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
static gen_helper_ldst_us * const fns[2][7][4] = {
/* masked unit stride load */
{ { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
{ NULL, gen_helper_vlh_v_h_mask,
gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
{ NULL, NULL,
gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
{ gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
{ gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
{ NULL, gen_helper_vlhu_v_h_mask,
gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
{ NULL, NULL,
gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
/* unmasked unit stride load */
{ { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
gen_helper_vlb_v_w, gen_helper_vlb_v_d },
{ NULL, gen_helper_vlh_v_h,
gen_helper_vlh_v_w, gen_helper_vlh_v_d },
{ NULL, NULL,
gen_helper_vlw_v_w, gen_helper_vlw_v_d },
{ gen_helper_vle_v_b, gen_helper_vle_v_h,
gen_helper_vle_v_w, gen_helper_vle_v_d },
{ gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
{ NULL, gen_helper_vlhu_v_h,
gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
{ NULL, NULL,
gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
};
fn = fns[a->vm][seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
static gen_helper_ldst_us * const fns[2][4][4] = {
/* masked unit stride load and store */
{ { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
{ NULL, gen_helper_vsh_v_h_mask,
gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
{ NULL, NULL,
gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
{ gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
/* unmasked unit stride store */
{ { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
gen_helper_vsb_v_w, gen_helper_vsb_v_d },
{ NULL, gen_helper_vsh_v_h,
gen_helper_vsh_v_w, gen_helper_vsh_v_d },
{ NULL, NULL,
gen_helper_vsw_v_w, gen_helper_vsw_v_d },
{ gen_helper_vse_v_b, gen_helper_vse_v_h,
gen_helper_vse_v_w, gen_helper_vse_v_d } }
};
fn = fns[a->vm][seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
/*
*** stride load and store
*/
typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
TCGv, TCGv_env, TCGv_i32);
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base, stride;
TCGv_i32 desc;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = tcg_temp_new();
stride = tcg_temp_new();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
gen_get_gpr(base, rs1);
gen_get_gpr(stride, rs2);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
fn(dest, mask, base, stride, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free(base);
tcg_temp_free(stride);
tcg_temp_free_i32(desc);
gen_set_label(over);
return true;
}
static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
static gen_helper_ldst_stride * const fns[7][4] = {
{ gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
{ NULL, gen_helper_vlsh_v_h,
gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
{ NULL, NULL,
gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
{ gen_helper_vlse_v_b, gen_helper_vlse_v_h,
gen_helper_vlse_v_w, gen_helper_vlse_v_d },
{ gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
{ NULL, gen_helper_vlshu_v_h,
gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
{ NULL, NULL,
gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
};
fn = fns[seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
static gen_helper_ldst_stride * const fns[4][4] = {
/* masked stride store */
{ gen_helper_vssb_v_b, gen_helper_vssb_v_h,
gen_helper_vssb_v_w, gen_helper_vssb_v_d },
{ NULL, gen_helper_vssh_v_h,
gen_helper_vssh_v_w, gen_helper_vssh_v_d },
{ NULL, NULL,
gen_helper_vssw_v_w, gen_helper_vssw_v_d },
{ gen_helper_vsse_v_b, gen_helper_vsse_v_h,
gen_helper_vsse_v_w, gen_helper_vsse_v_d }
};
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
fn = fns[seq][s->sew];
if (fn == NULL) {
return false;
}
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
target/riscv: add vector index load and store instructions Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:55 +00:00
/*
*** index load and store
*/
typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
TCGv_ptr, TCGv_env, TCGv_i32);
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn,
DisasContext *s)
{
TCGv_ptr dest, mask, index;
TCGv base;
TCGv_i32 desc;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
fn(dest, mask, base, index, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(index);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over);
return true;
}
static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[7][4] = {
{ gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
{ NULL, gen_helper_vlxh_v_h,
gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
{ NULL, NULL,
gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
{ gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
{ gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
{ NULL, gen_helper_vlxhu_v_h,
gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
{ NULL, NULL,
gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
};
fn = fns[seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_overlap_mask(s, a->rd, a->vm, false) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[4][4] = {
{ gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
{ NULL, gen_helper_vsxh_v_h,
gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
{ NULL, NULL,
gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
{ gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
};
fn = fns[seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_index_check(DisasContext *s, arg_rnfvm* a)
{
return (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
vext_check_nf(s, a->nf));
}
GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
target/riscv: add fault-only-first unit stride load The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-9-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:56 +00:00
/*
*** unit stride fault-only-first load
*/
static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
gen_helper_ldst_us *fn, DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base;
TCGv_i32 desc;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
fn(dest, mask, base, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over);
return true;
}
static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
static gen_helper_ldst_us * const fns[7][4] = {
{ gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
{ NULL, gen_helper_vlhff_v_h,
gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
{ NULL, NULL,
gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
{ gen_helper_vleff_v_b, gen_helper_vleff_v_h,
gen_helper_vleff_v_w, gen_helper_vleff_v_d },
{ gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
{ NULL, gen_helper_vlhuff_v_h,
gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
{ NULL, NULL,
gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
};
fn = fns[seq][s->sew];
if (fn == NULL) {
return false;
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldff_trans(a->rd, a->rs1, data, fn, s);
}
GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
target/riscv: add vector amo operations Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 15:24:57 +00:00
/*
*** vector atomic operation
*/
typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
TCGv_env, TCGv_i32);
static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_amo *fn, DisasContext *s)
{
TCGv_ptr dest, mask, index;
TCGv base;
TCGv_i32 desc;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
fn(dest, mask, base, index, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(index);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over);
return true;
}
static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_amo *fn;
static gen_helper_amo *const fnsw[9] = {
/* no atomic operation */
gen_helper_vamoswapw_v_w,
gen_helper_vamoaddw_v_w,
gen_helper_vamoxorw_v_w,
gen_helper_vamoandw_v_w,
gen_helper_vamoorw_v_w,
gen_helper_vamominw_v_w,
gen_helper_vamomaxw_v_w,
gen_helper_vamominuw_v_w,
gen_helper_vamomaxuw_v_w
};
#ifdef TARGET_RISCV64
static gen_helper_amo *const fnsd[18] = {
gen_helper_vamoswapw_v_d,
gen_helper_vamoaddw_v_d,
gen_helper_vamoxorw_v_d,
gen_helper_vamoandw_v_d,
gen_helper_vamoorw_v_d,
gen_helper_vamominw_v_d,
gen_helper_vamomaxw_v_d,
gen_helper_vamominuw_v_d,
gen_helper_vamomaxuw_v_d,
gen_helper_vamoswapd_v_d,
gen_helper_vamoaddd_v_d,
gen_helper_vamoxord_v_d,
gen_helper_vamoandd_v_d,
gen_helper_vamoord_v_d,
gen_helper_vamomind_v_d,
gen_helper_vamomaxd_v_d,
gen_helper_vamominud_v_d,
gen_helper_vamomaxud_v_d
};
#endif
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
} else {
if (s->sew == 3) {
#ifdef TARGET_RISCV64
fn = fnsd[seq];
#else
/* Check done in amo_check(). */
g_assert_not_reached();
#endif
} else {
fn = fnsw[seq];
}
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
/*
* There are two rules check here.
*
* 1. SEW must be at least as wide as the AMO memory element size.
*
* 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
*/
static bool amo_check(DisasContext *s, arg_rwdvm* a)
{
return (!s->vill && has_ext(s, RVA) &&
(!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
((1 << s->sew) <= sizeof(target_ulong)) &&
((1 << s->sew) >= 4));
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
#ifdef TARGET_RISCV64
GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
#endif