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Fix clock cycles in some arm/thumb opcodes. 

Implement missing ARM instruction used in the wstein.gba homebrew.
Remove cpuDmaHack has it causes graphical glitches in Lufia and incorrectly handles unmapped reads.

git-svn-id: https://svn.code.sf.net/p/vbam/code/trunk@1191 a31d4220-a93d-0410-bf67-fe4944624d44
This commit is contained in:
normmatt234 2013-04-06 08:51:58 +00:00
parent 4ea9fadeec
commit f4f7a5597f
4 changed files with 73 additions and 100 deletions
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15
src/gba/GBA-arm.cpp
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@ -1533,7 +1533,7 @@ static INSN_REGPARM void arm121(u32 opcode)
#define OP_LDR reg[dest].I = CPUReadMemory(address) #define OP_LDR reg[dest].I = CPUReadMemory(address)
#define OP_LDRH reg[dest].I = CPUReadHalfWord(address) #define OP_LDRH reg[dest].I = CPUReadHalfWord(address)
#define OP_LDRB reg[dest].I = CPUReadByte(address) #define OP_LDRB reg[dest].I = CPUReadByte(address)
#define OP_LDRSH reg[dest].I = (s16)CPUReadHalfWordSigned(address) #define OP_LDRSH reg[dest].I = (u32)CPUReadHalfWordSigned(address)
#define OP_LDRSB reg[dest].I = (s8)CPUReadByte(address) #define OP_LDRSB reg[dest].I = (s8)CPUReadByte(address)
#define WRITEBACK_NONE /*nothing*/ #define WRITEBACK_NONE /*nothing*/
@ -2608,8 +2608,7 @@ static INSN_REGPARM void armA00(u32 opcode)
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
clockTicks += 2 + codeTicksAccess32(armNextPC) clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
+ codeTicksAccessSeq32(armNextPC);
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2625,8 +2624,7 @@ static INSN_REGPARM void armB00(u32 opcode)
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
clockTicks += 2 + codeTicksAccess32(armNextPC) clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
+ codeTicksAccessSeq32(armNextPC);
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2644,9 +2642,8 @@ static INSN_REGPARM void armE01(u32 opcode)
// SWI <comment> // SWI <comment>
static INSN_REGPARM void armF00(u32 opcode) static INSN_REGPARM void armF00(u32 opcode)
{ {
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
clockTicks += 2 + codeTicksAccess32(armNextPC) clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
+ codeTicksAccessSeq32(armNextPC);
busPrefetchCount = 0; busPrefetchCount = 0;
CPUSoftwareInterrupt(opcode & 0x00FFFFFF); CPUSoftwareInterrupt(opcode & 0x00FFFFFF);
} }
@ -2700,7 +2697,7 @@ static insnfunc_t armInsnTable[4096] = {
arm0E0,arm0E1,arm0E2,arm0E3,arm0E4,arm0E5,arm0E6,arm0E7, // 0E0 arm0E0,arm0E1,arm0E2,arm0E3,arm0E4,arm0E5,arm0E6,arm0E7, // 0E0
arm0E0,arm0E9,arm0E2,arm0CB,arm0E4,arm_UI,arm0E6,arm_UI, // 0E8 arm0E0,arm0E9,arm0E2,arm0CB,arm0E4,arm_UI,arm0E6,arm_UI, // 0E8
arm0F0,arm0F1,arm0F2,arm0F3,arm0F4,arm0F5,arm0F6,arm0F7, // 0F0 arm0F0,arm0F1,arm0F2,arm0F3,arm0F4,arm0F5,arm0F6,arm0F7, // 0F0
arm0F0,arm0F9,arm0F2,arm_UI,arm0F4,arm0DD,arm0F6,arm0DF, // 0F8 arm0F0,arm0F9,arm0F2,arm0DB,arm0F4,arm0DD,arm0F6,arm0DF, // 0F8
arm100,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 100 arm100,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 100
arm_UI,arm109,arm_UI,arm10B,arm_UI,arm_UI,arm_UI,arm_UI, // 108 arm_UI,arm109,arm_UI,arm10B,arm_UI,arm_UI,arm_UI,arm_UI, // 108

79
src/gba/GBA-thumb.cpp
View File

@ -1421,12 +1421,14 @@ static INSN_REGPARM void thumb45_3(u32 opcode)
static INSN_REGPARM void thumb46_0(u32 opcode) static INSN_REGPARM void thumb46_0(u32 opcode)
{ {
reg[opcode&7].I = reg[((opcode>>3)&7)].I; reg[opcode&7].I = reg[((opcode>>3)&7)].I;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
} }
// MOV Rd, Hs // MOV Rd, Hs
static INSN_REGPARM void thumb46_1(u32 opcode) static INSN_REGPARM void thumb46_1(u32 opcode)
{ {
reg[opcode&7].I = reg[((opcode>>3)&7)+8].I; reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
} }
// MOV Hd, Rs // MOV Hd, Rs
@ -1473,16 +1475,14 @@ static INSN_REGPARM void thumb47(u32 opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
+ codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 3;
} else { } else {
armState = true; armState = true;
reg[15].I &= 0xFFFFFFFC; reg[15].I &= 0xFFFFFFFC;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) clockTicks = codeTicksAccessSeq32(armNextPC)*2 + codeTicksAccess32(armNextPC) + 3;
+ codeTicksAccessSeq32(armNextPC) + codeTicksAccess32(armNextPC) + 3;
} }
} }
@ -1576,7 +1576,7 @@ static INSN_REGPARM void thumb5E(u32 opcode)
if (busPrefetchCount == 0) if (busPrefetchCount == 0)
busPrefetch = busPrefetchEnable; busPrefetch = busPrefetchEnable;
u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I; u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
reg[opcode&7].I = (s16)CPUReadHalfWordSigned(address); reg[opcode&7].I = (u32)CPUReadHalfWordSigned(address);
clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
} }
@ -1669,6 +1669,7 @@ static INSN_REGPARM void thumbA0(u32 opcode)
{ {
u8 regist = (opcode >> 8) & 7; u8 regist = (opcode >> 8) & 7;
reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2); reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
clockTicks = 1 + codeTicksAccess16(armNextPC);
} }
// ADD R0~R7, SP, Imm // ADD R0~R7, SP, Imm
@ -1676,6 +1677,7 @@ static INSN_REGPARM void thumbA8(u32 opcode)
{ {
u8 regist = (opcode >> 8) & 7; u8 regist = (opcode >> 8) & 7;
reg[regist].I = reg[13].I + ((opcode&255)<<2); reg[regist].I = reg[13].I + ((opcode&255)<<2);
clockTicks = 1 + codeTicksAccess16(armNextPC);
} }
// ADD SP, Imm // ADD SP, Imm
@ -1685,6 +1687,7 @@ static INSN_REGPARM void thumbB0(u32 opcode)
if(opcode & 0x80) if(opcode & 0x80)
offset = -offset; offset = -offset;
reg[13].I += offset; reg[13].I += offset;
clockTicks = 1 + codeTicksAccess16(armNextPC);
} }
// Push and pop /////////////////////////////////////////////////////////// // Push and pop ///////////////////////////////////////////////////////////
@ -1882,13 +1885,13 @@ static INSN_REGPARM void thumbC8(u32 opcode)
static INSN_REGPARM void thumbD0(u32 opcode) static INSN_REGPARM void thumbD0(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(Z_FLAG) { if(Z_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1897,13 +1900,13 @@ static INSN_REGPARM void thumbD0(u32 opcode)
static INSN_REGPARM void thumbD1(u32 opcode) static INSN_REGPARM void thumbD1(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!Z_FLAG) { if(!Z_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1912,13 +1915,13 @@ static INSN_REGPARM void thumbD1(u32 opcode)
static INSN_REGPARM void thumbD2(u32 opcode) static INSN_REGPARM void thumbD2(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(C_FLAG) { if(C_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1927,13 +1930,13 @@ static INSN_REGPARM void thumbD2(u32 opcode)
static INSN_REGPARM void thumbD3(u32 opcode) static INSN_REGPARM void thumbD3(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!C_FLAG) { if(!C_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1942,13 +1945,13 @@ static INSN_REGPARM void thumbD3(u32 opcode)
static INSN_REGPARM void thumbD4(u32 opcode) static INSN_REGPARM void thumbD4(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG) { if(N_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1957,13 +1960,13 @@ static INSN_REGPARM void thumbD4(u32 opcode)
static INSN_REGPARM void thumbD5(u32 opcode) static INSN_REGPARM void thumbD5(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!N_FLAG) { if(!N_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1972,13 +1975,13 @@ static INSN_REGPARM void thumbD5(u32 opcode)
static INSN_REGPARM void thumbD6(u32 opcode) static INSN_REGPARM void thumbD6(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(V_FLAG) { if(V_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -1987,13 +1990,13 @@ static INSN_REGPARM void thumbD6(u32 opcode)
static INSN_REGPARM void thumbD7(u32 opcode) static INSN_REGPARM void thumbD7(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!V_FLAG) { if(!V_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2002,13 +2005,13 @@ static INSN_REGPARM void thumbD7(u32 opcode)
static INSN_REGPARM void thumbD8(u32 opcode) static INSN_REGPARM void thumbD8(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(C_FLAG && !Z_FLAG) { if(C_FLAG && !Z_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2017,13 +2020,13 @@ static INSN_REGPARM void thumbD8(u32 opcode)
static INSN_REGPARM void thumbD9(u32 opcode) static INSN_REGPARM void thumbD9(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!C_FLAG || Z_FLAG) { if(!C_FLAG || Z_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2032,13 +2035,13 @@ static INSN_REGPARM void thumbD9(u32 opcode)
static INSN_REGPARM void thumbDA(u32 opcode) static INSN_REGPARM void thumbDA(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG == V_FLAG) { if(N_FLAG == V_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2047,13 +2050,13 @@ static INSN_REGPARM void thumbDA(u32 opcode)
static INSN_REGPARM void thumbDB(u32 opcode) static INSN_REGPARM void thumbDB(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(N_FLAG != V_FLAG) { if(N_FLAG != V_FLAG) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2062,13 +2065,13 @@ static INSN_REGPARM void thumbDB(u32 opcode)
static INSN_REGPARM void thumbDC(u32 opcode) static INSN_REGPARM void thumbDC(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
if(!Z_FLAG && (N_FLAG == V_FLAG)) { if(!Z_FLAG && (N_FLAG == V_FLAG)) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2077,13 +2080,13 @@ static INSN_REGPARM void thumbDC(u32 opcode)
static INSN_REGPARM void thumbDD(u32 opcode) static INSN_REGPARM void thumbDD(u32 opcode)
{ {
UPDATE_OLDREG; UPDATE_OLDREG;
clockTicks = codeTicksAccessSeq16(armNextPC);
if(Z_FLAG || (N_FLAG != V_FLAG)) { if(Z_FLAG || (N_FLAG != V_FLAG)) {
reg[15].I += ((s8)(opcode & 0xFF)) << 1; reg[15].I += ((s8)(opcode & 0xFF)) << 1;
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
codeTicksAccess16(armNextPC)+3;
busPrefetchCount=0; busPrefetchCount=0;
} }
} }
@ -2094,8 +2097,8 @@ static INSN_REGPARM void thumbDD(u32 opcode)
static INSN_REGPARM void thumbDF(u32 opcode) static INSN_REGPARM void thumbDF(u32 opcode)
{ {
u32 address = 0; u32 address = 0;
clockTicks = codeTicksAccessSeq16(address) + codeTicksAccessSeq16(address) + //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
codeTicksAccess16(address)+3; clockTicks = 3;
busPrefetchCount=0; busPrefetchCount=0;
CPUSoftwareInterrupt(opcode & 0xFF); CPUSoftwareInterrupt(opcode & 0xFF);
} }
@ -2110,8 +2113,7 @@ static INSN_REGPARM void thumbE0(u32 opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 2; reg[15].I += 2;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) + clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC)+3;
codeTicksAccess16(armNextPC) + 3;
busPrefetchCount=0; busPrefetchCount=0;
} }
@ -2141,8 +2143,7 @@ static INSN_REGPARM void thumbF8(u32 opcode)
reg[15].I += 2; reg[15].I += 2;
reg[14].I = temp|1; reg[14].I = temp|1;
THUMB_PREFETCH; THUMB_PREFETCH;
clockTicks = codeTicksAccessSeq16(armNextPC) + clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
codeTicksAccess16(armNextPC) + codeTicksAccessSeq16(armNextPC) + 3;
busPrefetchCount = 0; busPrefetchCount = 0;
} }

18
src/gba/GBA.cpp
View File

@ -42,7 +42,6 @@ bool busPrefetchEnable = false;
u32 busPrefetchCount = 0; u32 busPrefetchCount = 0;
int cpuDmaTicksToUpdate = 0; int cpuDmaTicksToUpdate = 0;
int cpuDmaCount = 0; int cpuDmaCount = 0;
bool cpuDmaHack = false;
u32 cpuDmaLast = 0; u32 cpuDmaLast = 0;
int dummyAddress = 0; int dummyAddress = 0;
@ -934,7 +933,7 @@ bool CPUReadGSASnapshot(const char *fileName)
fseek(file, 0x0, SEEK_SET); fseek(file, 0x0, SEEK_SET);
fread(&i, 1, 4, file); fread(&i, 1, 4, file);
fseek(file, i, SEEK_CUR); // Skip SharkPortSave fseek(file, i, SEEK_CUR); // Skip SharkPortSave
fseek(file, 4, SEEK_CUR); // skip some sort of flag // fseek(file, 4, SEEK_CUR); // skip some sort of flag
fread(&i, 1, 4, file); // name length fread(&i, 1, 4, file); // name length
fseek(file, i, SEEK_CUR); // skip name fseek(file, i, SEEK_CUR); // skip name
fread(&i, 1, 4, file); // desc length fread(&i, 1, 4, file); // desc length
@ -1806,8 +1805,8 @@ void CPUSoftwareInterrupt(int comment)
case 0x02: case 0x02:
#ifdef GBA_LOGGING #ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_SWI) { if(systemVerbose & VERBOSE_SWI) {
log("Halt: (VCOUNT = %2d)\n", /*log("Halt: (VCOUNT = %2d)\n",
VCOUNT); VCOUNT);*/
} }
#endif #endif
holdState = true; holdState = true;
@ -1817,8 +1816,8 @@ void CPUSoftwareInterrupt(int comment)
case 0x03: case 0x03:
#ifdef GBA_LOGGING #ifdef GBA_LOGGING
if(systemVerbose & VERBOSE_SWI) { if(systemVerbose & VERBOSE_SWI) {
log("Stop: (VCOUNT = %2d)\n", /*log("Stop: (VCOUNT = %2d)\n",
VCOUNT); VCOUNT);*/
} }
#endif #endif
holdState = true; holdState = true;
@ -2184,7 +2183,6 @@ void CPUCheckDMA(int reason, int dmamask)
doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement, doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement,
DM0CNT_L ? DM0CNT_L : 0x4000, DM0CNT_L ? DM0CNT_L : 0x4000,
DM0CNT_H & 0x0400); DM0CNT_H & 0x0400);
cpuDmaHack = true;
if(DM0CNT_H & 0x4000) { if(DM0CNT_H & 0x4000) {
IF |= 0x0100; IF |= 0x0100;
@ -2253,7 +2251,6 @@ void CPUCheckDMA(int reason, int dmamask)
DM1CNT_L ? DM1CNT_L : 0x4000, DM1CNT_L ? DM1CNT_L : 0x4000,
DM1CNT_H & 0x0400); DM1CNT_H & 0x0400);
} }
cpuDmaHack = true;
if(DM1CNT_H & 0x4000) { if(DM1CNT_H & 0x4000) {
IF |= 0x0200; IF |= 0x0200;
@ -2323,7 +2320,6 @@ void CPUCheckDMA(int reason, int dmamask)
DM2CNT_L ? DM2CNT_L : 0x4000, DM2CNT_L ? DM2CNT_L : 0x4000,
DM2CNT_H & 0x0400); DM2CNT_H & 0x0400);
} }
cpuDmaHack = true;
if(DM2CNT_H & 0x4000) { if(DM2CNT_H & 0x4000) {
IF |= 0x0400; IF |= 0x0400;
@ -3404,8 +3400,6 @@ void CPUReset()
systemSaveUpdateCounter = SYSTEM_SAVE_NOT_UPDATED; systemSaveUpdateCounter = SYSTEM_SAVE_NOT_UPDATED;
cpuDmaHack = false;
lastTime = systemGetClock(); lastTime = systemGetClock();
SWITicks = 0; SWITicks = 0;
@ -3504,7 +3498,6 @@ void CPULoop(int ticks)
clockTicks = cpuNextEvent; clockTicks = cpuNextEvent;
cpuTotalTicks = 0; cpuTotalTicks = 0;
cpuDmaHack = false;
updateLoop: updateLoop:
@ -3906,7 +3899,6 @@ void CPULoop(int ticks)
cpuDmaTicksToUpdate -= clockTicks; cpuDmaTicksToUpdate -= clockTicks;
if(cpuDmaTicksToUpdate < 0) if(cpuDmaTicksToUpdate < 0)
cpuDmaTicksToUpdate = 0; cpuDmaTicksToUpdate = 0;
cpuDmaHack = true;
goto updateLoop; goto updateLoop;
} }

61
src/gba/GBAinline.h
View File

@ -19,7 +19,6 @@ extern bool cpuSramEnabled;
extern bool cpuFlashEnabled; extern bool cpuFlashEnabled;
extern bool cpuEEPROMEnabled; extern bool cpuEEPROMEnabled;
extern bool cpuEEPROMSensorEnabled; extern bool cpuEEPROMSensorEnabled;
extern bool cpuDmaHack;
extern u32 cpuDmaLast; extern u32 cpuDmaLast;
extern bool timer0On; extern bool timer0On;
extern int timer0Ticks; extern int timer0Ticks;
@ -49,11 +48,9 @@ static inline u32 CPUReadMemory(u32 address)
u32 value; u32 value;
u32 oldAddress = address; u32 oldAddress = address;
#ifdef C_CORE
if(address & 3) { if(address & 3) {
address &= ~0x03; address &= ~0x03;
} }
#endif
switch(address >> 24) { switch(address >> 24) {
case 0: case 0:
@ -133,18 +130,12 @@ unreadable:
armNextPC - 4 : armNextPC - 2); armNextPC - 4 : armNextPC - 2);
} }
#endif #endif
if(armState) {
if(cpuDmaHack) { return CPUReadMemoryQuick(reg[15].I);
value = cpuDmaLast;
} else { } else {
if(armState) { return CPUReadHalfWordQuick(reg[15].I) |
value = CPUReadMemoryQuick(reg[15].I); CPUReadHalfWordQuick(reg[15].I) << 16;
} else {
value = CPUReadHalfWordQuick(reg[15].I) |
CPUReadHalfWordQuick(reg[15].I) << 16;
}
} }
return value;
} }
if(oldAddress & 3) { if(oldAddress & 3) {
@ -187,11 +178,9 @@ static inline u32 CPUReadHalfWord(u32 address)
u32 value; u32 value;
u32 oldAddress = address; u32 oldAddress = address;
//#ifdef C_CORE
if(address & 1) { if(address & 1) {
address &= ~0x01; address &= ~0x01;
} }
//#endif
switch(address >> 24) { switch(address >> 24) {
case 0: case 0:
@ -280,17 +269,12 @@ unreadable:
armNextPC - 4 : armNextPC - 2); armNextPC - 4 : armNextPC - 2);
} }
#endif #endif
if(cpuDmaHack) { if(armState) {
value = cpuDmaLast & 0xFFFF; return CPUReadMemoryQuick(reg[15].I);
} else { } else {
if(armState) { return CPUReadHalfWordQuick(reg[15].I) |
value = CPUReadMemoryQuick(reg[15].I); CPUReadHalfWordQuick(reg[15].I) << 16;
} else { }
value = CPUReadHalfWordQuick(reg[15].I) |
CPUReadHalfWordQuick(reg[15].I) << 16;
}
}
return value;
} }
if(oldAddress & 1) { if(oldAddress & 1) {
@ -306,13 +290,13 @@ unreadable:
return value; return value;
} }
static inline u16 CPUReadHalfWordSigned(u32 address) static inline s16 CPUReadHalfWordSigned(u32 address)
{ {
u32 oldAddress = address; u32 oldAddress = address;
if(address & 1) { if(address & 1) {
address &= ~0x01; address &= ~0x01;
} }
u16 value = CPUReadHalfWord(address); s16 value = (s16)CPUReadHalfWord(address);
if((oldAddress & 1)) if((oldAddress & 1))
{ {
value = (s8)value; value = (s8)value;
@ -395,17 +379,12 @@ unreadable:
armNextPC - 4 : armNextPC - 2); armNextPC - 4 : armNextPC - 2);
} }
#endif #endif
if(cpuDmaHack) { if(armState) {
return cpuDmaLast & 0xFF; return CPUReadMemoryQuick(reg[15].I);
} else { } else {
if(armState) { return CPUReadHalfWordQuick(reg[15].I) |
return CPUReadMemoryQuick(reg[15].I); CPUReadHalfWordQuick(reg[15].I) << 16;
} else { }
return CPUReadHalfWordQuick(reg[15].I) |
CPUReadHalfWordQuick(reg[15].I) << 16;
}
}
break;
} }
} }
@ -423,6 +402,8 @@ static inline void CPUWriteMemory(u32 address, u32 value)
} }
#endif #endif
address &= 0xFFFFFFFC;
switch(address >> 24) { switch(address >> 24) {
case 0x02: case 0x02:
#ifdef BKPT_SUPPORT #ifdef BKPT_SUPPORT
@ -520,6 +501,8 @@ static inline void CPUWriteHalfWord(u32 address, u16 value)
} }
#endif #endif
address &= 0xFFFFFFFE;
switch(address >> 24) { switch(address >> 24) {
case 2: case 2:
#ifdef BKPT_SUPPORT #ifdef BKPT_SUPPORT