diff --git a/src/gba/GBA-arm.cpp b/src/gba/GBA-arm.cpp
index cc711bc9..6063ce46 100644
--- a/src/gba/GBA-arm.cpp
+++ b/src/gba/GBA-arm.cpp
@@ -754,12 +754,16 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_LSL_REG_C
  #define VALUE_LSL_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	unsigned int rm = reg[opcode & 0x0F].I;             \
+	if(opcode & 0x0F == 15) {                           \
+		rm += 4;                                        \
+	}                                                   \
     if (LIKELY(shift)) {                                \
         if (shift == 32) {                              \
             value = 0;                                  \
-            C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\
+            C_OUT = (rm & 1 ? true : false);\
         } else if (LIKELY(shift < 32)) {                \
-            u32 v = reg[opcode & 0x0F].I;               \
+            u32 v = rm;               \
             C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
             value = v << shift;                         \
         } else {                                        \
@@ -767,7 +771,7 @@ static void count(u32 opcode, int cond_res)
             C_OUT = false;                              \
         }                                               \
     } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+        value = rm;                   \
     }
 #endif
 // OP Rd,Rb,Rm LSR #
@@ -787,20 +791,23 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_LSR_REG_C
  #define VALUE_LSR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	unsigned int rm = reg[opcode & 0x0F].I;             \
+	if(opcode & 0x0F == 15) {                           \
+		rm += 4;                                        \
+	}                                                   \
     if (LIKELY(shift)) {                                \
         if (shift == 32) {                              \
             value = 0;                                  \
-            C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\
+            C_OUT = (rm & 0x80000000 ? true : false);   \
         } else if (LIKELY(shift < 32)) {                \
-            u32 v = reg[opcode & 0x0F].I;               \
-            C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
-            value = v >> shift;                         \
+            C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\
+            value = rm >> shift;                        \
         } else {                                        \
             value = 0;                                  \
             C_OUT = false;                              \
         }                                               \
     } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+        value = rm;                   \
     }
 #endif
 // OP Rd,Rb,Rm ASR #
@@ -826,16 +833,19 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_ASR_REG_C
  #define VALUE_ASR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	unsigned int rm = reg[opcode & 0x0F].I;             \
+	if(opcode & 0x0F == 15) {                           \
+		rm += 4;                                        \
+	}                                                   \
     if (LIKELY(shift < 32)) {                           \
         if (LIKELY(shift)) {                            \
-            s32 v = reg[opcode & 0x0F].I;               \
-            C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
-            value = v >> (int)shift;                    \
+            C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\
+            value = rm >> (int)shift;                   \
         } else {                                        \
-            value = reg[opcode & 0x0F].I;               \
+            value = rm;                                 \
         }                                               \
     } else {                                            \
-        if (reg[opcode & 0x0F].I & 0x80000000) {        \
+        if (rm & 0x80000000) {                          \
             value = 0xFFFFFFFF;                         \
             C_OUT = true;                               \
         } else {                                        \
@@ -864,13 +874,16 @@ static void count(u32 opcode, int cond_res)
 #ifndef VALUE_ROR_REG_C
  #define VALUE_ROR_REG_C \
     unsigned int shift = reg[(opcode >> 8)&15].B.B0;    \
+	unsigned int rm = reg[opcode & 0x0F].I;             \
+	if(opcode & 0x0F == 15) {                           \
+		rm += 4;                                        \
+	}                                                   \
     if (LIKELY(shift & 0x1F)) {                         \
-        u32 v = reg[opcode & 0x0F].I;                   \
-        C_OUT = (v >> (shift - 1)) & 1 ? true : false;  \
-        value = ((v << (32 - shift)) |                  \
-                 (v >> shift));                         \
+        C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \
+        value = ((rm << (32 - shift)) |                 \
+                 (rm >> shift));                        \
     } else {                                            \
-        value = reg[opcode & 0x0F].I;                   \
+        value = rm;                                     \
         if (shift)                                      \
             C_OUT = (value & 0x80000000 ? true : false);\
     }
@@ -951,9 +964,8 @@ static void count(u32 opcode, int cond_res)
 #endif
 #ifndef OP_RSB
  #define OP_RSB \
-    u32 lhs = reg[(opcode>>16)&15].I;                   \
-    u32 rhs = value;                                    \
-    u32 res = rhs - lhs;                                \
+    u32 lhs = value;                                    \
+    u32 rhs = reg[(opcode>>16)&15].I;                   \
     reg[dest].I = res;
 #endif
 #ifndef OP_RSBS
@@ -2947,4 +2959,4 @@ int armExecute()
     } while (cpuTotalTicks<cpuNextEvent && armState && !holdState && !SWITicks);
 
     return 1;
-}
+}
\ No newline at end of file