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Fix clock cycle count for MUL, MLA instructions... (b91f39c787) 

- backport Fix clock cycle count for some arm/thumb instructions (5243b2d806)
- backport Fix base cycle count for MUL, MLA series (b91f39c787)
This commit is contained in:
negativeExponent 2020-08-11 21:05:17 +08:00
parent c07d5b658b
commit d9732f68db
2 changed files with 12 additions and 15 deletions
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11
src/gba/GBA-arm.cpp
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@ -1251,7 +1251,7 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES)
clockTicks += 3; \ clockTicks += 3; \
if (busPrefetchCount == 0) \ if (busPrefetchCount == 0) \
busPrefetchCount = ((busPrefetchCount + 1) << clockTicks) - 1; \ busPrefetchCount = ((busPrefetchCount + 1) << clockTicks) - 1; \
clockTicks += 1 + codeTicksAccess32(armNextPC); clockTicks += CYCLES + 1 + codeTicksAccess32(armNextPC);
#define OP_MUL \ #define OP_MUL \
reg[dest].I = reg[mult].I * rs; reg[dest].I = reg[mult].I * rs;
@ -2581,8 +2581,7 @@ static INSN_REGPARM void armA00(uint32_t opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2595,8 +2594,7 @@ static INSN_REGPARM void armB00(uint32_t opcode)
armNextPC = reg[15].I; armNextPC = reg[15].I;
reg[15].I += 4; reg[15].I += 4;
ARM_PREFETCH; ARM_PREFETCH;
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
} }
@ -2612,8 +2610,7 @@ static INSN_REGPARM void armE01(uint32_t opcode)
// SWI <comment> // SWI <comment>
static INSN_REGPARM void armF00(uint32_t opcode) static INSN_REGPARM void armF00(uint32_t opcode)
{ {
clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (codeTicksAccessSeq32(armNextPC) * 2) + codeTicksAccess32(armNextPC) + 3;
clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
busPrefetchCount = 0; busPrefetchCount = 0;
CPUSoftwareInterrupt(opcode & 0x00FFFFFF); CPUSoftwareInterrupt(opcode & 0x00FFFFFF);
} }

16
src/gba/GBA-thumb.cpp
View File

@ -1146,9 +1146,9 @@ static INSN_REGPARM void thumb43_1(uint32_t opcode)
reg[dest].I = reg[(opcode >> 3) & 7].I * rm; reg[dest].I = reg[(opcode >> 3) & 7].I * rm;
if (((int32_t)rm) < 0) if (((int32_t)rm) < 0)
rm = ~rm; rm = ~rm;
if ((rm & 0xFFFFFF00) == 0) if ((rm & 0xFFFFFF00) == 0) {
clockTicks += 0; // clockTicks += 0;
else if ((rm & 0xFFFF0000) == 0) } else if ((rm & 0xFFFF0000) == 0)
clockTicks += 1; clockTicks += 1;
else if ((rm & 0xFF000000) == 0) else if ((rm & 0xFF000000) == 0)
clockTicks += 2; clockTicks += 2;
@ -1594,7 +1594,7 @@ static INSN_REGPARM void thumbBC(uint32_t opcode)
POP_REG(64, 6); POP_REG(64, 6);
POP_REG(128, 7); POP_REG(128, 7);
reg[13].I = temp; reg[13].I = temp;
clockTicks = 2 + codeTicksAccess16(armNextPC); clockTicks += 2 + codeTicksAccess16(armNextPC);
} }
// POP {Rlist, PC} // POP {Rlist, PC}
@ -1625,7 +1625,7 @@ static INSN_REGPARM void thumbBD(uint32_t opcode)
reg[13].I = temp; reg[13].I = temp;
THUMB_PREFETCH; THUMB_PREFETCH;
busPrefetchCount = 0; busPrefetchCount = 0;
clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC); clockTicks += 3 + (codeTicksAccess16(armNextPC) * 2);
} }
// Load/store multiple //////////////////////////////////////////////////// // Load/store multiple ////////////////////////////////////////////////////
@ -1673,7 +1673,7 @@ static INSN_REGPARM void thumbC0(uint32_t opcode)
THUMB_STM_REG(32, 5, regist); THUMB_STM_REG(32, 5, regist);
THUMB_STM_REG(64, 6, regist); THUMB_STM_REG(64, 6, regist);
THUMB_STM_REG(128, 7, regist); THUMB_STM_REG(128, 7, regist);
clockTicks = 1 + codeTicksAccess16(armNextPC); clockTicks += 1 + codeTicksAccess16(armNextPC);
} }
// LDM R0~R7!, {Rlist} // LDM R0~R7!, {Rlist}
@ -1694,7 +1694,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
THUMB_LDM_REG(32, 5); THUMB_LDM_REG(32, 5);
THUMB_LDM_REG(64, 6); THUMB_LDM_REG(64, 6);
THUMB_LDM_REG(128, 7); THUMB_LDM_REG(128, 7);
clockTicks = 2 + codeTicksAccess16(armNextPC); clockTicks += 2 + codeTicksAccess16(armNextPC);
if (!(opcode & (1 << regist))) if (!(opcode & (1 << regist)))
reg[regist].I = temp; reg[regist].I = temp;
} }
@ -1703,7 +1703,7 @@ static INSN_REGPARM void thumbC8(uint32_t opcode)
#define THUMB_CONDITIONAL_BRANCH(COND) \ #define THUMB_CONDITIONAL_BRANCH(COND) \
UPDATE_OLDREG; \ UPDATE_OLDREG; \
clockTicks = codeTicksAccessSeq16(armNextPC) + 1; \ clockTicks = codeTicksAccessSeq16(armNextPC) + 1; \
if (COND) { \ if ((bool)COND) { \
uint32_t offset = (uint32_t)((int8_t)(opcode & 0xFF)) << 1; \ uint32_t offset = (uint32_t)((int8_t)(opcode & 0xFF)) << 1; \
reg[15].I += offset; \ reg[15].I += offset; \
armNextPC = reg[15].I; \ armNextPC = reg[15].I; \