Fix yet another oversight in the unaligned read code.
Implemented missing thumb opcode (Which is invalid according to gbatek but Moto GP seems to use it)
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@ -1417,6 +1417,12 @@ static INSN_REGPARM void thumb45_3(u32 opcode)
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CMP_RD_RS;
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}
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// MOV Rd, Rs
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static INSN_REGPARM void thumb46_0(u32 opcode)
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{
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reg[opcode&7].I = reg[((opcode>>3)&7)].I;
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}
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// MOV Rd, Hs
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static INSN_REGPARM void thumb46_1(u32 opcode)
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{
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@ -2185,7 +2191,7 @@ static insnfunc_t thumbInsnTable[1024] = {
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thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3, // 40
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thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3,
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thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3,
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thumbUI,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
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thumb46_0,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI,
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thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48, // 48
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thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
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thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,
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@ -149,9 +149,8 @@ unreadable:
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break;
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}
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if(address & 3) {
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if(oldAddress & 3) {
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#ifdef C_CORE
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int shift = (address & 3) << 3;
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value = (value >> shift) | (value << (32 - shift));
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#else
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#ifdef __GNUC__
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