From ba3083b538058b03dcefb35bb449ed70a3d7c4ce Mon Sep 17 00:00:00 2001 From: Zach Bacon Date: Sat, 9 Jul 2016 22:08:20 -0400 Subject: [PATCH] Expect more of these type of messages till all is done --- src/gba/GBA-arm.cpp | 762 +++++++++++++++++++++--------------------- src/gba/GBAcpu.h | 40 +-- src/gba/gbafilter.cpp | 10 +- src/gba/gbafilter.h | 6 +- 4 files changed, 409 insertions(+), 409 deletions(-) diff --git a/src/gba/GBA-arm.cpp b/src/gba/GBA-arm.cpp index fa049c06..e00837b1 100644 --- a/src/gba/GBA-arm.cpp +++ b/src/gba/GBA-arm.cpp @@ -38,7 +38,7 @@ static int clockTicks; -static INSN_REGPARM void armUnknownInsn(u32 opcode) +static INSN_REGPARM void armUnknownInsn(uint32_t opcode) { #ifdef GBA_LOGGING if (systemVerbose & VERBOSE_UNDEFINED) { @@ -50,7 +50,7 @@ static INSN_REGPARM void armUnknownInsn(u32 opcode) } #ifdef BKPT_SUPPORT -static INSN_REGPARM void armBreakpoint(u32 opcode) +static INSN_REGPARM void armBreakpoint(uint32_t opcode) { reg[15].I -= 4; armNextPC -= 4; @@ -62,7 +62,7 @@ static INSN_REGPARM void armBreakpoint(u32 opcode) // Subroutine to count instructions (for debugging/optimizing) //#define INSN_COUNTER // comment out if you don't want it #ifdef INSN_COUNTER -static void count(u32 opcode, int cond_res) +static void count(uint32_t opcode, int cond_res) { static int insncount = 0; // number of insns seen static int executed = 0; // number of insns executed @@ -711,16 +711,16 @@ static void count(u32 opcode, int cond_res) // C core #define C_SETCOND_LOGICAL \ - N_FLAG = ((s32)res < 0) ? true : false; \ + N_FLAG = ((int32_t)res < 0) ? true : false; \ Z_FLAG = (res == 0) ? true : false; \ C_FLAG = C_OUT; #define C_SETCOND_ADD \ - N_FLAG = ((s32)res < 0) ? true : false; \ + N_FLAG = ((int32_t)res < 0) ? true : false; \ Z_FLAG = (res == 0) ? true : false; \ V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) | (POS(lhs) & POS(rhs) & NEG(res))) ? true : false; \ C_FLAG = ((NEG(lhs) & NEG(rhs)) | (NEG(lhs) & POS(res)) | (NEG(rhs) & POS(res))) ? true : false; #define C_SETCOND_SUB \ - N_FLAG = ((s32)res < 0) ? true : false; \ + N_FLAG = ((int32_t)res < 0) ? true : false; \ Z_FLAG = (res == 0) ? true : false; \ V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))) ? true : false; \ C_FLAG = ((NEG(lhs) & POS(rhs)) | (NEG(lhs) & POS(res)) | (POS(rhs) & POS(res))) ? true : false; @@ -729,7 +729,7 @@ static void count(u32 opcode, int cond_res) #define ALU_INIT_C \ int dest = (opcode >> 12) & 15; \ bool C_OUT = C_FLAG; \ - u32 value; + uint32_t value; #endif // OP Rd,Rb,Rm LSL # #ifndef VALUE_LSL_IMM_C @@ -738,7 +738,7 @@ static void count(u32 opcode, int cond_res) if (LIKELY(!shift)) { /* LSL #0 most common? */ \ value = reg[opcode & 0x0F].I; \ } else { \ - u32 v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ value = v << shift; \ } @@ -746,8 +746,8 @@ static void count(u32 opcode, int cond_res) // OP Rd,Rb,Rm LSL Rs #ifndef VALUE_LSL_REG_C #define VALUE_LSL_REG_C \ - u32 shift = reg[(opcode >> 8) & 15].B.B0; \ - u32 rm = reg[opcode & 0x0F].I; \ + uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ @@ -756,7 +756,7 @@ static void count(u32 opcode, int cond_res) value = 0; \ C_OUT = (rm & 1 ? true : false); \ } else if (LIKELY(shift < 32)) { \ - u32 v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ value = v << shift; \ } else { \ @@ -770,9 +770,9 @@ static void count(u32 opcode, int cond_res) // OP Rd,Rb,Rm LSR # #ifndef VALUE_LSR_IMM_C #define VALUE_LSR_IMM_C \ - u32 shift = (opcode >> 7) & 0x1F; \ + uint32_t shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ - u32 v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = v >> shift; \ } else { \ @@ -784,7 +784,7 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_LSR_REG_C #define VALUE_LSR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - u32 rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ @@ -793,7 +793,7 @@ static void count(u32 opcode, int cond_res) value = 0; \ C_OUT = (rm & 0x80000000 ? true : false); \ } else if (LIKELY(shift < 32)) { \ - u32 v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = v >> shift; \ } else { \ @@ -809,8 +809,8 @@ static void count(u32 opcode, int cond_res) #define VALUE_ASR_IMM_C \ unsigned int shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ - /* VC++ BUG: u32 v; (s32)v>>n is optimized to shr! */ \ - s32 v = reg[opcode & 0x0F].I; \ + /* VC++ BUG: uint32_t v; (int32_t)v>>n is optimized to shr! */ \ + int32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false; \ value = v >> (int)shift; \ } else { \ @@ -827,13 +827,13 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_ASR_REG_C #define VALUE_ASR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - u32 rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ if (LIKELY(shift < 32)) { \ if (LIKELY(shift)) { \ - s32 v = rm; \ + int32_t v = rm; \ C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false; \ value = v >> (int)shift; \ } else { \ @@ -854,11 +854,11 @@ static void count(u32 opcode, int cond_res) #define VALUE_ROR_IMM_C \ unsigned int shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ - u32 v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ - u32 v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v & 1) ? true : false; \ value = ((v >> 1) | (C_FLAG << 31)); \ } @@ -867,12 +867,12 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_ROR_REG_C #define VALUE_ROR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - u32 rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ if (LIKELY(shift & 0x1F)) { \ - u32 v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ @@ -886,7 +886,7 @@ static void count(u32 opcode, int cond_res) #define VALUE_IMM_C \ int shift = (opcode & 0xF00) >> 7; \ if (UNLIKELY(shift)) { \ - u32 v = opcode & 0xFF; \ + uint32_t v = opcode & 0xFF; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ @@ -933,7 +933,7 @@ static void count(u32 opcode, int cond_res) } #ifndef OP_AND #define OP_AND \ - u32 res = reg[(opcode >> 16) & 15].I & value; \ + uint32_t res = reg[(opcode >> 16) & 15].I & value; \ reg[dest].I = res; #endif #ifndef OP_ANDS @@ -941,7 +941,7 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_EOR #define OP_EOR \ - u32 res = reg[(opcode >> 16) & 15].I ^ value; \ + uint32_t res = reg[(opcode >> 16) & 15].I ^ value; \ reg[dest].I = res; #endif #ifndef OP_EORS @@ -949,9 +949,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_SUB #define OP_SUB \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs - rhs; \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs - rhs; \ reg[dest].I = res; #endif #ifndef OP_SUBS @@ -959,9 +959,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_RSB #define OP_RSB \ - u32 lhs = value; \ - u32 rhs = reg[(opcode >> 16) & 15].I; \ - u32 res = lhs - rhs; \ + uint32_t lhs = value; \ + uint32_t rhs = reg[(opcode >> 16) & 15].I; \ + uint32_t res = lhs - rhs; \ reg[dest].I = res; #endif #ifndef OP_RSBS @@ -969,9 +969,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_ADD #define OP_ADD \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs + rhs; \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs; \ reg[dest].I = res; #endif #ifndef OP_ADDS @@ -979,9 +979,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_ADC #define OP_ADC \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs + rhs + (u32)C_FLAG; \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \ reg[dest].I = res; #endif #ifndef OP_ADCS @@ -989,9 +989,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_SBC #define OP_SBC \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs - rhs - !((u32)C_FLAG); \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \ reg[dest].I = res; #endif #ifndef OP_SBCS @@ -999,9 +999,9 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_RSC #define OP_RSC \ - u32 lhs = value; \ - u32 rhs = reg[(opcode >> 16) & 15].I; \ - u32 res = lhs - rhs - !((u32)C_FLAG); \ + uint32_t lhs = value; \ + uint32_t rhs = reg[(opcode >> 16) & 15].I; \ + uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \ reg[dest].I = res; #endif #ifndef OP_RSCS @@ -1009,31 +1009,31 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_TST #define OP_TST \ - u32 res = reg[(opcode >> 16) & 0x0F].I & value; \ + uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \ C_SETCOND_LOGICAL; #endif #ifndef OP_TEQ #define OP_TEQ \ - u32 res = reg[(opcode >> 16) & 0x0F].I ^ value; \ + uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \ C_SETCOND_LOGICAL; #endif #ifndef OP_CMP #define OP_CMP \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs - rhs; \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs - rhs; \ C_SETCOND_SUB; #endif #ifndef OP_CMN #define OP_CMN \ - u32 lhs = reg[(opcode >> 16) & 15].I; \ - u32 rhs = value; \ - u32 res = lhs + rhs; \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs; \ C_SETCOND_ADD; #endif #ifndef OP_ORR #define OP_ORR \ - u32 res = reg[(opcode >> 16) & 0x0F].I | value; \ + uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \ reg[dest].I = res; #endif #ifndef OP_ORRS @@ -1041,7 +1041,7 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_MOV #define OP_MOV \ - u32 res = value; \ + uint32_t res = value; \ reg[dest].I = res; #endif #ifndef OP_MOVS @@ -1049,7 +1049,7 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_BIC #define OP_BIC \ - u32 res = reg[(opcode >> 16) & 0x0F].I & (~value); \ + uint32_t res = reg[(opcode >> 16) & 0x0F].I & (~value); \ reg[dest].I = res; #endif #ifndef OP_BICS @@ -1057,7 +1057,7 @@ static void count(u32 opcode, int cond_res) #endif #ifndef OP_MVN #define OP_MVN \ - u32 res = ~value; \ + uint32_t res = ~value; \ reg[dest].I = res; #endif #ifndef OP_MVNS @@ -1069,7 +1069,7 @@ static void count(u32 opcode, int cond_res) #endif #ifndef SETCOND_MUL #define SETCOND_MUL \ - N_FLAG = ((s32)reg[dest].I < 0) ? true : false; \ + N_FLAG = ((int32_t)reg[dest].I < 0) ? true : false; \ Z_FLAG = reg[dest].I ? false : true; #endif #ifndef SETCOND_MULL @@ -1084,7 +1084,7 @@ static void count(u32 opcode, int cond_res) #ifndef ROR_IMM_MSR #define ROR_IMM_MSR \ - u32 v = opcode & 0xff; \ + uint32_t v = opcode & 0xff; \ value = ((v << (32 - shift)) | (v >> shift)); #endif #ifndef ROR_OFFSET @@ -1132,25 +1132,25 @@ static void count(u32 opcode, int cond_res) #define MODECHANGE_YES CPUSwitchMode(reg[17].I & 0x1f, false); #define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \ - static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } + static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } #define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \ - static INSN_REGPARM void arm##CODE1##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##1(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##2(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##3(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##4(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##5(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE1##6(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ - static INSN_REGPARM void arm##CODE1##7(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ - static INSN_REGPARM void arm##CODE2##0(u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } + static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##3(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##4(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##5(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ + static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ + static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } // AND DEFINE_ALU_INSN_NC(00, 20, AND, NO) @@ -1231,12 +1231,12 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES) // CYCLES: base cycle count (1, 2, or 3) #define MUL_INSN(OP, SETCOND, CYCLES) \ int mult = (opcode & 0x0F); \ - u32 rs = reg[(opcode >> 8) & 0x0F].I; \ + uint32_t rs = reg[(opcode >> 8) & 0x0F].I; \ int acc = (opcode >> 12) & 0x0F; /* or destLo */ \ int dest = (opcode >> 16) & 0x0F; /* or destHi */ \ OP; \ SETCOND; \ - if ((s32)rs < 0) \ + if ((int32_t)rs < 0) \ rs = ~rs; \ if ((rs & 0xFFFFFF00) == 0) \ clockTicks += 0; \ @@ -1257,56 +1257,56 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES) #define OP_MULL(SIGN) \ SIGN##64 res = (SIGN##64)(SIGN##32)reg[mult].I \ * (SIGN##64)(SIGN##32)rs; \ - reg[acc].I = (u32)res; \ - reg[dest].I = (u32)(res >> 32); + reg[acc].I = (uint32_t)res; \ + reg[dest].I = (uint32_t)(res >> 32); #define OP_MLAL(SIGN) \ SIGN##64 res = ((SIGN##64)reg[dest].I << 32 | reg[acc].I) \ + ((SIGN##64)(SIGN##32)reg[mult].I \ * (SIGN##64)(SIGN##32)rs); \ - reg[acc].I = (u32)res; \ - reg[dest].I = (u32)(res >> 32); + reg[acc].I = (uint32_t)res; \ + reg[dest].I = (uint32_t)(res >> 32); #define OP_UMULL OP_MULL(u) #define OP_UMLAL OP_MLAL(u) #define OP_SMULL OP_MULL(s) #define OP_SMLAL OP_MLAL(s) // MUL Rd, Rm, Rs -static INSN_REGPARM void arm009(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); } +static INSN_REGPARM void arm009(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); } // MULS Rd, Rm, Rs -static INSN_REGPARM void arm019(u32 opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); } +static INSN_REGPARM void arm019(uint32_t opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); } // MLA Rd, Rm, Rs, Rn -static INSN_REGPARM void arm029(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); } +static INSN_REGPARM void arm029(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); } // MLAS Rd, Rm, Rs, Rn -static INSN_REGPARM void arm039(u32 opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); } +static INSN_REGPARM void arm039(uint32_t opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); } // UMULL RdLo, RdHi, Rn, Rs -static INSN_REGPARM void arm089(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); } +static INSN_REGPARM void arm089(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); } // UMULLS RdLo, RdHi, Rn, Rs -static INSN_REGPARM void arm099(u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); } +static INSN_REGPARM void arm099(uint32_t opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); } // UMLAL RdLo, RdHi, Rn, Rs -static INSN_REGPARM void arm0A9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); } +static INSN_REGPARM void arm0A9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); } // UMLALS RdLo, RdHi, Rn, Rs -static INSN_REGPARM void arm0B9(u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); } +static INSN_REGPARM void arm0B9(uint32_t opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); } // SMULL RdLo, RdHi, Rm, Rs -static INSN_REGPARM void arm0C9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); } +static INSN_REGPARM void arm0C9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); } // SMULLS RdLo, RdHi, Rm, Rs -static INSN_REGPARM void arm0D9(u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); } +static INSN_REGPARM void arm0D9(uint32_t opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); } // SMLAL RdLo, RdHi, Rm, Rs -static INSN_REGPARM void arm0E9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); } +static INSN_REGPARM void arm0E9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); } // SMLALS RdLo, RdHi, Rm, Rs -static INSN_REGPARM void arm0F9(u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); } +static INSN_REGPARM void arm0F9(uint32_t opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); } // Misc instructions ////////////////////////////////////////////////////// // SWP Rd, Rm, [Rn] -static INSN_REGPARM void arm109(u32 opcode) +static INSN_REGPARM void arm109(uint32_t opcode) { - u32 address = reg[(opcode >> 16) & 15].I; - u32 temp = CPUReadMemory(address); + uint32_t address = reg[(opcode >> 16) & 15].I; + uint32_t temp = CPUReadMemory(address); CPUWriteMemory(address, reg[opcode & 15].I); reg[(opcode >> 12) & 15].I = temp; clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address) @@ -1314,10 +1314,10 @@ static INSN_REGPARM void arm109(u32 opcode) } // SWPB Rd, Rm, [Rn] -static INSN_REGPARM void arm149(u32 opcode) +static INSN_REGPARM void arm149(uint32_t opcode) { - u32 address = reg[(opcode >> 16) & 15].I; - u32 temp = CPUReadByte(address); + uint32_t address = reg[(opcode >> 16) & 15].I; + uint32_t temp = CPUReadByte(address); CPUWriteByte(address, reg[opcode & 15].B.B0); reg[(opcode >> 12) & 15].I = temp; clockTicks = 4 + dataTicksAccess32(address) + dataTicksAccess32(address) @@ -1325,7 +1325,7 @@ static INSN_REGPARM void arm149(u32 opcode) } // MRS Rd, CPSR -static INSN_REGPARM void arm100(u32 opcode) +static INSN_REGPARM void arm100(uint32_t opcode) { if (LIKELY((opcode & 0x0FFF0FFF) == 0x010F0000)) { CPUUpdateCPSR(); @@ -1336,7 +1336,7 @@ static INSN_REGPARM void arm100(u32 opcode) } // MRS Rd, SPSR -static INSN_REGPARM void arm140(u32 opcode) +static INSN_REGPARM void arm140(uint32_t opcode) { if (LIKELY((opcode & 0x0FFF0FFF) == 0x014F0000)) { reg[(opcode >> 12) & 0x0F].I = reg[17].I; @@ -1346,12 +1346,12 @@ static INSN_REGPARM void arm140(u32 opcode) } // MSR CPSR_fields, Rm -static INSN_REGPARM void arm120(u32 opcode) +static INSN_REGPARM void arm120(uint32_t opcode) { if (LIKELY((opcode & 0x0FF0FFF0) == 0x0120F000)) { CPUUpdateCPSR(); - u32 value = reg[opcode & 15].I; - u32 newValue = reg[16].I; + uint32_t value = reg[opcode & 15].I; + uint32_t newValue = reg[16].I; if (armMode > 0x10) { if (opcode & 0x00010000) newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF); @@ -1376,10 +1376,10 @@ static INSN_REGPARM void arm120(u32 opcode) } // MSR SPSR_fields, Rm -static INSN_REGPARM void arm160(u32 opcode) +static INSN_REGPARM void arm160(uint32_t opcode) { if (LIKELY((opcode & 0x0FF0FFF0) == 0x0160F000)) { - u32 value = reg[opcode & 15].I; + uint32_t value = reg[opcode & 15].I; if (armMode > 0x10 && armMode < 0x1F) { if (opcode & 0x00010000) reg[17].I = (reg[17].I & 0xFFFFFF00) | (value & 0x000000FF); @@ -1396,16 +1396,16 @@ static INSN_REGPARM void arm160(u32 opcode) } // MSR CPSR_fields, # -static INSN_REGPARM void arm320(u32 opcode) +static INSN_REGPARM void arm320(uint32_t opcode) { if (LIKELY((opcode & 0x0FF0F000) == 0x0320F000)) { CPUUpdateCPSR(); - u32 value = opcode & 0xFF; + uint32_t value = opcode & 0xFF; int shift = (opcode & 0xF00) >> 7; if (shift) { ROR_IMM_MSR; } - u32 newValue = reg[16].I; + uint32_t newValue = reg[16].I; if (armMode > 0x10) { if (opcode & 0x00010000) newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF); @@ -1432,11 +1432,11 @@ static INSN_REGPARM void arm320(u32 opcode) } // MSR SPSR_fields, # -static INSN_REGPARM void arm360(u32 opcode) +static INSN_REGPARM void arm360(uint32_t opcode) { if (LIKELY((opcode & 0x0FF0F000) == 0x0360F000)) { if (armMode > 0x10 && armMode < 0x1F) { - u32 value = opcode & 0xFF; + uint32_t value = opcode & 0xFF; int shift = (opcode & 0xF00) >> 7; if (shift) { ROR_IMM_MSR; @@ -1456,7 +1456,7 @@ static INSN_REGPARM void arm360(u32 opcode) } // BX Rm -static INSN_REGPARM void arm121(u32 opcode) +static INSN_REGPARM void arm121(uint32_t opcode) { if (LIKELY((opcode & 0x0FFFFFF0) == 0x012FFF10)) { int base = opcode & 0x0F; @@ -1501,14 +1501,14 @@ static INSN_REGPARM void arm121(u32 opcode) int shift = (opcode >> 7) & 31; \ int offset; \ if (shift) \ - offset = (int)((s32)reg[opcode & 15].I >> shift); \ + offset = (int)((int32_t)reg[opcode & 15].I >> shift); \ else if (reg[opcode & 15].I & 0x80000000) \ offset = 0xFFFFFFFF; \ else \ offset = 0; #define OFFSET_ROR \ int shift = (opcode >> 7) & 31; \ - u32 offset = reg[opcode & 15].I; \ + uint32_t offset = reg[opcode & 15].I; \ if (shift) { \ ROR_OFFSET; \ } else { \ @@ -1525,8 +1525,8 @@ static INSN_REGPARM void arm121(u32 opcode) #define OP_LDR reg[dest].I = CPUReadMemory(address) #define OP_LDRH reg[dest].I = CPUReadHalfWord(address) #define OP_LDRB reg[dest].I = CPUReadByte(address) -#define OP_LDRSH reg[dest].I = (u32)CPUReadHalfWordSigned(address) -#define OP_LDRSB reg[dest].I = (s8)CPUReadByte(address) +#define OP_LDRSH reg[dest].I = (uint32_t)CPUReadHalfWordSigned(address) +#define OP_LDRSB reg[dest].I = (int8_t)CPUReadByte(address) #define WRITEBACK_NONE /*nothing*/ #define WRITEBACK_PRE reg[base].I = address @@ -1539,7 +1539,7 @@ static INSN_REGPARM void arm121(u32 opcode) int dest = (opcode >> 12) & 15; \ int base = (opcode >> 16) & 15; \ CALC_OFFSET; \ - u32 address = CALC_ADDRESS; + uint32_t address = CALC_ADDRESS; #define STR(CALC_OFFSET, CALC_ADDRESS, STORE_DATA, WRITEBACK1, WRITEBACK2, SIZE) \ LDRSTR_INIT(CALC_OFFSET, CALC_ADDRESS); \ @@ -1591,347 +1591,347 @@ static INSN_REGPARM void arm121(u32 opcode) LDR(CALC_OFFSET, ADDRESS_PREINC, LOAD_DATA, WRITEBACK_PRE, SIZE) // STRH Rd, [Rn], -Rm -static INSN_REGPARM void arm00B(u32 opcode) { STR_POSTDEC(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm00B(uint32_t opcode) { STR_POSTDEC(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn], #-offset -static INSN_REGPARM void arm04B(u32 opcode) { STR_POSTDEC(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm04B(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM8, OP_STRH, 16); } // STRH Rd, [Rn], Rm -static INSN_REGPARM void arm08B(u32 opcode) { STR_POSTINC(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm08B(uint32_t opcode) { STR_POSTINC(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn], #offset -static INSN_REGPARM void arm0CB(u32 opcode) { STR_POSTINC(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm0CB(uint32_t opcode) { STR_POSTINC(OFFSET_IMM8, OP_STRH, 16); } // STRH Rd, [Rn, -Rm] -static INSN_REGPARM void arm10B(u32 opcode) { STR_PREDEC(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm10B(uint32_t opcode) { STR_PREDEC(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn, -Rm]! -static INSN_REGPARM void arm12B(u32 opcode) { STR_PREDEC_WB(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm12B(uint32_t opcode) { STR_PREDEC_WB(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn, -#offset] -static INSN_REGPARM void arm14B(u32 opcode) { STR_PREDEC(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm14B(uint32_t opcode) { STR_PREDEC(OFFSET_IMM8, OP_STRH, 16); } // STRH Rd, [Rn, -#offset]! -static INSN_REGPARM void arm16B(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm16B(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM8, OP_STRH, 16); } // STRH Rd, [Rn, Rm] -static INSN_REGPARM void arm18B(u32 opcode) { STR_PREINC(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm18B(uint32_t opcode) { STR_PREINC(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn, Rm]! -static INSN_REGPARM void arm1AB(u32 opcode) { STR_PREINC_WB(OFFSET_REG, OP_STRH, 16); } +static INSN_REGPARM void arm1AB(uint32_t opcode) { STR_PREINC_WB(OFFSET_REG, OP_STRH, 16); } // STRH Rd, [Rn, #offset] -static INSN_REGPARM void arm1CB(u32 opcode) { STR_PREINC(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm1CB(uint32_t opcode) { STR_PREINC(OFFSET_IMM8, OP_STRH, 16); } // STRH Rd, [Rn, #offset]! -static INSN_REGPARM void arm1EB(u32 opcode) { STR_PREINC_WB(OFFSET_IMM8, OP_STRH, 16); } +static INSN_REGPARM void arm1EB(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM8, OP_STRH, 16); } // LDRH Rd, [Rn], -Rm -static INSN_REGPARM void arm01B(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm01B(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn], #-offset -static INSN_REGPARM void arm05B(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm05B(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRH, 16); } // LDRH Rd, [Rn], Rm -static INSN_REGPARM void arm09B(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm09B(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn], #offset -static INSN_REGPARM void arm0DB(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm0DB(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRH, 16); } // LDRH Rd, [Rn, -Rm] -static INSN_REGPARM void arm11B(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm11B(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn, -Rm]! -static INSN_REGPARM void arm13B(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm13B(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn, -#offset] -static INSN_REGPARM void arm15B(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm15B(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRH, 16); } // LDRH Rd, [Rn, -#offset]! -static INSN_REGPARM void arm17B(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm17B(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRH, 16); } // LDRH Rd, [Rn, Rm] -static INSN_REGPARM void arm19B(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm19B(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn, Rm]! -static INSN_REGPARM void arm1BB(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRH, 16); } +static INSN_REGPARM void arm1BB(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRH, 16); } // LDRH Rd, [Rn, #offset] -static INSN_REGPARM void arm1DB(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm1DB(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRH, 16); } // LDRH Rd, [Rn, #offset]! -static INSN_REGPARM void arm1FB(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRH, 16); } +static INSN_REGPARM void arm1FB(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRH, 16); } // LDRSB Rd, [Rn], -Rm -static INSN_REGPARM void arm01D(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm01D(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn], #-offset -static INSN_REGPARM void arm05D(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm05D(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSB Rd, [Rn], Rm -static INSN_REGPARM void arm09D(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm09D(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn], #offset -static INSN_REGPARM void arm0DD(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm0DD(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSB Rd, [Rn, -Rm] -static INSN_REGPARM void arm11D(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm11D(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn, -Rm]! -static INSN_REGPARM void arm13D(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm13D(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn, -#offset] -static INSN_REGPARM void arm15D(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm15D(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSB Rd, [Rn, -#offset]! -static INSN_REGPARM void arm17D(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm17D(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSB Rd, [Rn, Rm] -static INSN_REGPARM void arm19D(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm19D(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn, Rm]! -static INSN_REGPARM void arm1BD(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSB, 16); } +static INSN_REGPARM void arm1BD(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSB, 16); } // LDRSB Rd, [Rn, #offset] -static INSN_REGPARM void arm1DD(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm1DD(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSB Rd, [Rn, #offset]! -static INSN_REGPARM void arm1FD(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSB, 16); } +static INSN_REGPARM void arm1FD(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSB, 16); } // LDRSH Rd, [Rn], -Rm -static INSN_REGPARM void arm01F(u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm01F(uint32_t opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn], #-offset -static INSN_REGPARM void arm05F(u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm05F(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSH, 16); } // LDRSH Rd, [Rn], Rm -static INSN_REGPARM void arm09F(u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm09F(uint32_t opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn], #offset -static INSN_REGPARM void arm0DF(u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm0DF(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSH, 16); } // LDRSH Rd, [Rn, -Rm] -static INSN_REGPARM void arm11F(u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm11F(uint32_t opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn, -Rm]! -static INSN_REGPARM void arm13F(u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm13F(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn, -#offset] -static INSN_REGPARM void arm15F(u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm15F(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSH, 16); } // LDRSH Rd, [Rn, -#offset]! -static INSN_REGPARM void arm17F(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm17F(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSH, 16); } // LDRSH Rd, [Rn, Rm] -static INSN_REGPARM void arm19F(u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm19F(uint32_t opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn, Rm]! -static INSN_REGPARM void arm1BF(u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSH, 16); } +static INSN_REGPARM void arm1BF(uint32_t opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSH, 16); } // LDRSH Rd, [Rn, #offset] -static INSN_REGPARM void arm1DF(u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm1DF(uint32_t opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSH, 16); } // LDRSH Rd, [Rn, #offset]! -static INSN_REGPARM void arm1FF(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSH, 16); } +static INSN_REGPARM void arm1FF(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSH, 16); } // STR[T] Rd, [Rn], -# // Note: STR and STRT do the same thing on the GBA (likewise for LDR/LDRT etc) -static INSN_REGPARM void arm400(u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm400(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM, OP_STR, 32); } // LDR[T] Rd, [Rn], -# -static INSN_REGPARM void arm410(u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm410(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDR, 32); } // STRB[T] Rd, [Rn], -# -static INSN_REGPARM void arm440(u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm440(uint32_t opcode) { STR_POSTDEC(OFFSET_IMM, OP_STRB, 16); } // LDRB[T] Rd, [Rn], -# -static INSN_REGPARM void arm450(u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm450(uint32_t opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDRB, 16); } // STR[T] Rd, [Rn], # -static INSN_REGPARM void arm480(u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm480(uint32_t opcode) { STR_POSTINC(OFFSET_IMM, OP_STR, 32); } // LDR Rd, [Rn], # -static INSN_REGPARM void arm490(u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm490(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDR, 32); } // STRB[T] Rd, [Rn], # -static INSN_REGPARM void arm4C0(u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm4C0(uint32_t opcode) { STR_POSTINC(OFFSET_IMM, OP_STRB, 16); } // LDRB[T] Rd, [Rn], # -static INSN_REGPARM void arm4D0(u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm4D0(uint32_t opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDRB, 16); } // STR Rd, [Rn, -#] -static INSN_REGPARM void arm500(u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm500(uint32_t opcode) { STR_PREDEC(OFFSET_IMM, OP_STR, 32); } // LDR Rd, [Rn, -#] -static INSN_REGPARM void arm510(u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm510(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDR, 32); } // STR Rd, [Rn, -#]! -static INSN_REGPARM void arm520(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm520(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STR, 32); } // LDR Rd, [Rn, -#]! -static INSN_REGPARM void arm530(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm530(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDR, 32); } // STRB Rd, [Rn, -#] -static INSN_REGPARM void arm540(u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm540(uint32_t opcode) { STR_PREDEC(OFFSET_IMM, OP_STRB, 16); } // LDRB Rd, [Rn, -#] -static INSN_REGPARM void arm550(u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm550(uint32_t opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDRB, 16); } // STRB Rd, [Rn, -#]! -static INSN_REGPARM void arm560(u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm560(uint32_t opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STRB, 16); } // LDRB Rd, [Rn, -#]! -static INSN_REGPARM void arm570(u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm570(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDRB, 16); } // STR Rd, [Rn, #] -static INSN_REGPARM void arm580(u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm580(uint32_t opcode) { STR_PREINC(OFFSET_IMM, OP_STR, 32); } // LDR Rd, [Rn, #] -static INSN_REGPARM void arm590(u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm590(uint32_t opcode) { LDR_PREINC(OFFSET_IMM, OP_LDR, 32); } // STR Rd, [Rn, #]! -static INSN_REGPARM void arm5A0(u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STR, 32); } +static INSN_REGPARM void arm5A0(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STR, 32); } // LDR Rd, [Rn, #]! -static INSN_REGPARM void arm5B0(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDR, 32); } +static INSN_REGPARM void arm5B0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDR, 32); } // STRB Rd, [Rn, #] -static INSN_REGPARM void arm5C0(u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm5C0(uint32_t opcode) { STR_PREINC(OFFSET_IMM, OP_STRB, 16); } // LDRB Rd, [Rn, #] -static INSN_REGPARM void arm5D0(u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm5D0(uint32_t opcode) { LDR_PREINC(OFFSET_IMM, OP_LDRB, 16); } // STRB Rd, [Rn, #]! -static INSN_REGPARM void arm5E0(u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STRB, 16); } +static INSN_REGPARM void arm5E0(uint32_t opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STRB, 16); } // LDRB Rd, [Rn, #]! -static INSN_REGPARM void arm5F0(u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDRB, 16); } +static INSN_REGPARM void arm5F0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDRB, 16); } // STR[T] Rd, [Rn], -Rm, LSL # -static INSN_REGPARM void arm600(u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm600(uint32_t opcode) { STR_POSTDEC(OFFSET_LSL, OP_STR, 32); } // STR[T] Rd, [Rn], -Rm, LSR # -static INSN_REGPARM void arm602(u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm602(uint32_t opcode) { STR_POSTDEC(OFFSET_LSR, OP_STR, 32); } // STR[T] Rd, [Rn], -Rm, ASR # -static INSN_REGPARM void arm604(u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm604(uint32_t opcode) { STR_POSTDEC(OFFSET_ASR, OP_STR, 32); } // STR[T] Rd, [Rn], -Rm, ROR # -static INSN_REGPARM void arm606(u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm606(uint32_t opcode) { STR_POSTDEC(OFFSET_ROR, OP_STR, 32); } // LDR[T] Rd, [Rn], -Rm, LSL # -static INSN_REGPARM void arm610(u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm610(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDR, 32); } // LDR[T] Rd, [Rn], -Rm, LSR # -static INSN_REGPARM void arm612(u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm612(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDR, 32); } // LDR[T] Rd, [Rn], -Rm, ASR # -static INSN_REGPARM void arm614(u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm614(uint32_t opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDR, 32); } // LDR[T] Rd, [Rn], -Rm, ROR # -static INSN_REGPARM void arm616(u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm616(uint32_t opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDR, 32); } // STRB[T] Rd, [Rn], -Rm, LSL # -static INSN_REGPARM void arm640(u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm640(uint32_t opcode) { STR_POSTDEC(OFFSET_LSL, OP_STRB, 16); } // STRB[T] Rd, [Rn], -Rm, LSR # -static INSN_REGPARM void arm642(u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm642(uint32_t opcode) { STR_POSTDEC(OFFSET_LSR, OP_STRB, 16); } // STRB[T] Rd, [Rn], -Rm, ASR # -static INSN_REGPARM void arm644(u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm644(uint32_t opcode) { STR_POSTDEC(OFFSET_ASR, OP_STRB, 16); } // STRB[T] Rd, [Rn], -Rm, ROR # -static INSN_REGPARM void arm646(u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm646(uint32_t opcode) { STR_POSTDEC(OFFSET_ROR, OP_STRB, 16); } // LDRB[T] Rd, [Rn], -Rm, LSL # -static INSN_REGPARM void arm650(u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm650(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDRB, 16); } // LDRB[T] Rd, [Rn], -Rm, LSR # -static INSN_REGPARM void arm652(u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm652(uint32_t opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDRB, 16); } // LDRB[T] Rd, [Rn], -Rm, ASR # -static INSN_REGPARM void arm654(u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm654(uint32_t opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDRB, 16); } // LDRB Rd, [Rn], -Rm, ROR # -static INSN_REGPARM void arm656(u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm656(uint32_t opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDRB, 16); } // STR[T] Rd, [Rn], Rm, LSL # -static INSN_REGPARM void arm680(u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm680(uint32_t opcode) { STR_POSTINC(OFFSET_LSL, OP_STR, 32); } // STR[T] Rd, [Rn], Rm, LSR # -static INSN_REGPARM void arm682(u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm682(uint32_t opcode) { STR_POSTINC(OFFSET_LSR, OP_STR, 32); } // STR[T] Rd, [Rn], Rm, ASR # -static INSN_REGPARM void arm684(u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm684(uint32_t opcode) { STR_POSTINC(OFFSET_ASR, OP_STR, 32); } // STR[T] Rd, [Rn], Rm, ROR # -static INSN_REGPARM void arm686(u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm686(uint32_t opcode) { STR_POSTINC(OFFSET_ROR, OP_STR, 32); } // LDR[T] Rd, [Rn], Rm, LSL # -static INSN_REGPARM void arm690(u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm690(uint32_t opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDR, 32); } // LDR[T] Rd, [Rn], Rm, LSR # -static INSN_REGPARM void arm692(u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm692(uint32_t opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDR, 32); } // LDR[T] Rd, [Rn], Rm, ASR # -static INSN_REGPARM void arm694(u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm694(uint32_t opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDR, 32); } // LDR[T] Rd, [Rn], Rm, ROR # -static INSN_REGPARM void arm696(u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm696(uint32_t opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDR, 32); } // STRB[T] Rd, [Rn], Rm, LSL # -static INSN_REGPARM void arm6C0(u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm6C0(uint32_t opcode) { STR_POSTINC(OFFSET_LSL, OP_STRB, 16); } // STRB[T] Rd, [Rn], Rm, LSR # -static INSN_REGPARM void arm6C2(u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm6C2(uint32_t opcode) { STR_POSTINC(OFFSET_LSR, OP_STRB, 16); } // STRB[T] Rd, [Rn], Rm, ASR # -static INSN_REGPARM void arm6C4(u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm6C4(uint32_t opcode) { STR_POSTINC(OFFSET_ASR, OP_STRB, 16); } // STRB[T] Rd, [Rn], Rm, ROR # -static INSN_REGPARM void arm6C6(u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm6C6(uint32_t opcode) { STR_POSTINC(OFFSET_ROR, OP_STRB, 16); } // LDRB[T] Rd, [Rn], Rm, LSL # -static INSN_REGPARM void arm6D0(u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm6D0(uint32_t opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDRB, 16); } // LDRB[T] Rd, [Rn], Rm, LSR # -static INSN_REGPARM void arm6D2(u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm6D2(uint32_t opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDRB, 16); } // LDRB[T] Rd, [Rn], Rm, ASR # -static INSN_REGPARM void arm6D4(u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm6D4(uint32_t opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDRB, 16); } // LDRB[T] Rd, [Rn], Rm, ROR # -static INSN_REGPARM void arm6D6(u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm6D6(uint32_t opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDRB, 16); } // STR Rd, [Rn, -Rm, LSL #] -static INSN_REGPARM void arm700(u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm700(uint32_t opcode) { STR_PREDEC(OFFSET_LSL, OP_STR, 32); } // STR Rd, [Rn, -Rm, LSR #] -static INSN_REGPARM void arm702(u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm702(uint32_t opcode) { STR_PREDEC(OFFSET_LSR, OP_STR, 32); } // STR Rd, [Rn, -Rm, ASR #] -static INSN_REGPARM void arm704(u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm704(uint32_t opcode) { STR_PREDEC(OFFSET_ASR, OP_STR, 32); } // STR Rd, [Rn, -Rm, ROR #] -static INSN_REGPARM void arm706(u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm706(uint32_t opcode) { STR_PREDEC(OFFSET_ROR, OP_STR, 32); } // LDR Rd, [Rn, -Rm, LSL #] -static INSN_REGPARM void arm710(u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm710(uint32_t opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, LSR #] -static INSN_REGPARM void arm712(u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm712(uint32_t opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, ASR #] -static INSN_REGPARM void arm714(u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm714(uint32_t opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, ROR #] -static INSN_REGPARM void arm716(u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm716(uint32_t opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDR, 32); } // STR Rd, [Rn, -Rm, LSL #]! -static INSN_REGPARM void arm720(u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm720(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STR, 32); } // STR Rd, [Rn, -Rm, LSR #]! -static INSN_REGPARM void arm722(u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm722(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STR, 32); } // STR Rd, [Rn, -Rm, ASR #]! -static INSN_REGPARM void arm724(u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm724(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STR, 32); } // STR Rd, [Rn, -Rm, ROR #]! -static INSN_REGPARM void arm726(u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm726(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STR, 32); } // LDR Rd, [Rn, -Rm, LSL #]! -static INSN_REGPARM void arm730(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm730(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, LSR #]! -static INSN_REGPARM void arm732(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm732(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, ASR #]! -static INSN_REGPARM void arm734(u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm734(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDR, 32); } // LDR Rd, [Rn, -Rm, ROR #]! -static INSN_REGPARM void arm736(u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm736(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDR, 32); } // STRB Rd, [Rn, -Rm, LSL #] -static INSN_REGPARM void arm740(u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm740(uint32_t opcode) { STR_PREDEC(OFFSET_LSL, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, LSR #] -static INSN_REGPARM void arm742(u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm742(uint32_t opcode) { STR_PREDEC(OFFSET_LSR, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, ASR #] -static INSN_REGPARM void arm744(u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm744(uint32_t opcode) { STR_PREDEC(OFFSET_ASR, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, ROR #] -static INSN_REGPARM void arm746(u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm746(uint32_t opcode) { STR_PREDEC(OFFSET_ROR, OP_STRB, 16); } // LDRB Rd, [Rn, -Rm, LSL #] -static INSN_REGPARM void arm750(u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm750(uint32_t opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, LSR #] -static INSN_REGPARM void arm752(u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm752(uint32_t opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, ASR #] -static INSN_REGPARM void arm754(u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm754(uint32_t opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, ROR #] -static INSN_REGPARM void arm756(u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm756(uint32_t opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDRB, 16); } // STRB Rd, [Rn, -Rm, LSL #]! -static INSN_REGPARM void arm760(u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm760(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, LSR #]! -static INSN_REGPARM void arm762(u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm762(uint32_t opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, ASR #]! -static INSN_REGPARM void arm764(u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm764(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STRB, 16); } // STRB Rd, [Rn, -Rm, ROR #]! -static INSN_REGPARM void arm766(u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm766(uint32_t opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STRB, 16); } // LDRB Rd, [Rn, -Rm, LSL #]! -static INSN_REGPARM void arm770(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm770(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, LSR #]! -static INSN_REGPARM void arm772(u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm772(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, ASR #]! -static INSN_REGPARM void arm774(u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm774(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDRB, 16); } // LDRB Rd, [Rn, -Rm, ROR #]! -static INSN_REGPARM void arm776(u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm776(uint32_t opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDRB, 16); } // STR Rd, [Rn, Rm, LSL #] -static INSN_REGPARM void arm780(u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm780(uint32_t opcode) { STR_PREINC(OFFSET_LSL, OP_STR, 32); } // STR Rd, [Rn, Rm, LSR #] -static INSN_REGPARM void arm782(u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm782(uint32_t opcode) { STR_PREINC(OFFSET_LSR, OP_STR, 32); } // STR Rd, [Rn, Rm, ASR #] -static INSN_REGPARM void arm784(u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm784(uint32_t opcode) { STR_PREINC(OFFSET_ASR, OP_STR, 32); } // STR Rd, [Rn, Rm, ROR #] -static INSN_REGPARM void arm786(u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm786(uint32_t opcode) { STR_PREINC(OFFSET_ROR, OP_STR, 32); } // LDR Rd, [Rn, Rm, LSL #] -static INSN_REGPARM void arm790(u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm790(uint32_t opcode) { LDR_PREINC(OFFSET_LSL, OP_LDR, 32); } // LDR Rd, [Rn, Rm, LSR #] -static INSN_REGPARM void arm792(u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm792(uint32_t opcode) { LDR_PREINC(OFFSET_LSR, OP_LDR, 32); } // LDR Rd, [Rn, Rm, ASR #] -static INSN_REGPARM void arm794(u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm794(uint32_t opcode) { LDR_PREINC(OFFSET_ASR, OP_LDR, 32); } // LDR Rd, [Rn, Rm, ROR #] -static INSN_REGPARM void arm796(u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm796(uint32_t opcode) { LDR_PREINC(OFFSET_ROR, OP_LDR, 32); } // STR Rd, [Rn, Rm, LSL #]! -static INSN_REGPARM void arm7A0(u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STR, 32); } +static INSN_REGPARM void arm7A0(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STR, 32); } // STR Rd, [Rn, Rm, LSR #]! -static INSN_REGPARM void arm7A2(u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STR, 32); } +static INSN_REGPARM void arm7A2(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STR, 32); } // STR Rd, [Rn, Rm, ASR #]! -static INSN_REGPARM void arm7A4(u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STR, 32); } +static INSN_REGPARM void arm7A4(uint32_t opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STR, 32); } // STR Rd, [Rn, Rm, ROR #]! -static INSN_REGPARM void arm7A6(u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STR, 32); } +static INSN_REGPARM void arm7A6(uint32_t opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STR, 32); } // LDR Rd, [Rn, Rm, LSL #]! -static INSN_REGPARM void arm7B0(u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDR, 32); } +static INSN_REGPARM void arm7B0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDR, 32); } // LDR Rd, [Rn, Rm, LSR #]! -static INSN_REGPARM void arm7B2(u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDR, 32); } +static INSN_REGPARM void arm7B2(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDR, 32); } // LDR Rd, [Rn, Rm, ASR #]! -static INSN_REGPARM void arm7B4(u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDR, 32); } +static INSN_REGPARM void arm7B4(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDR, 32); } // LDR Rd, [Rn, Rm, ROR #]! -static INSN_REGPARM void arm7B6(u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDR, 32); } +static INSN_REGPARM void arm7B6(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDR, 32); } // STRB Rd, [Rn, Rm, LSL #] -static INSN_REGPARM void arm7C0(u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm7C0(uint32_t opcode) { STR_PREINC(OFFSET_LSL, OP_STRB, 16); } // STRB Rd, [Rn, Rm, LSR #] -static INSN_REGPARM void arm7C2(u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm7C2(uint32_t opcode) { STR_PREINC(OFFSET_LSR, OP_STRB, 16); } // STRB Rd, [Rn, Rm, ASR #] -static INSN_REGPARM void arm7C4(u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm7C4(uint32_t opcode) { STR_PREINC(OFFSET_ASR, OP_STRB, 16); } // STRB Rd, [Rn, Rm, ROR #] -static INSN_REGPARM void arm7C6(u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm7C6(uint32_t opcode) { STR_PREINC(OFFSET_ROR, OP_STRB, 16); } // LDRB Rd, [Rn, Rm, LSL #] -static INSN_REGPARM void arm7D0(u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm7D0(uint32_t opcode) { LDR_PREINC(OFFSET_LSL, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, LSR #] -static INSN_REGPARM void arm7D2(u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm7D2(uint32_t opcode) { LDR_PREINC(OFFSET_LSR, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, ASR #] -static INSN_REGPARM void arm7D4(u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm7D4(uint32_t opcode) { LDR_PREINC(OFFSET_ASR, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, ROR #] -static INSN_REGPARM void arm7D6(u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm7D6(uint32_t opcode) { LDR_PREINC(OFFSET_ROR, OP_LDRB, 16); } // STRB Rd, [Rn, Rm, LSL #]! -static INSN_REGPARM void arm7E0(u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STRB, 16); } +static INSN_REGPARM void arm7E0(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STRB, 16); } // STRB Rd, [Rn, Rm, LSR #]! -static INSN_REGPARM void arm7E2(u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STRB, 16); } +static INSN_REGPARM void arm7E2(uint32_t opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STRB, 16); } // STRB Rd, [Rn, Rm, ASR #]! -static INSN_REGPARM void arm7E4(u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STRB, 16); } +static INSN_REGPARM void arm7E4(uint32_t opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STRB, 16); } // STRB Rd, [Rn, Rm, ROR #]! -static INSN_REGPARM void arm7E6(u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STRB, 16); } +static INSN_REGPARM void arm7E6(uint32_t opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STRB, 16); } // LDRB Rd, [Rn, Rm, LSL #]! -static INSN_REGPARM void arm7F0(u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDRB, 16); } +static INSN_REGPARM void arm7F0(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, LSR #]! -static INSN_REGPARM void arm7F2(u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDRB, 16); } +static INSN_REGPARM void arm7F2(uint32_t opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, ASR #]! -static INSN_REGPARM void arm7F4(u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDRB, 16); } +static INSN_REGPARM void arm7F4(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDRB, 16); } // LDRB Rd, [Rn, Rm, ROR #]! -static INSN_REGPARM void arm7F6(u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, 16); } +static INSN_REGPARM void arm7F6(uint32_t opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, 16); } // STM/LDM //////////////////////////////////////////////////////////////// @@ -2130,52 +2130,52 @@ static INSN_REGPARM void arm7F6(u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, } // STMDA Rn, {Rlist} -static INSN_REGPARM void arm800(u32 opcode) +static INSN_REGPARM void arm800(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; STM_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDA Rn, {Rlist} -static INSN_REGPARM void arm810(u32 opcode) +static INSN_REGPARM void arm810(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); } // STMDA Rn!, {Rlist} -static INSN_REGPARM void arm820(u32 opcode) +static INSN_REGPARM void arm820(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; STMW_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDA Rn!, {Rlist} -static INSN_REGPARM void arm830(u32 opcode) +static INSN_REGPARM void arm830(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); @@ -2184,26 +2184,26 @@ static INSN_REGPARM void arm830(u32 opcode) } // STMDA Rn, {Rlist}^ -static INSN_REGPARM void arm840(u32 opcode) +static INSN_REGPARM void arm840(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; STM_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDA Rn, {Rlist}^ -static INSN_REGPARM void arm850(u32 opcode) +static INSN_REGPARM void arm850(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL_2; LDM_ALL_2B; @@ -2211,26 +2211,26 @@ static INSN_REGPARM void arm850(u32 opcode) } // STMDA Rn!, {Rlist}^ -static INSN_REGPARM void arm860(u32 opcode) +static INSN_REGPARM void arm860(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; STMW_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDA Rn!, {Rlist}^ -static INSN_REGPARM void arm870(u32 opcode) +static INSN_REGPARM void arm870(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (temp + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (temp + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL_2; if (!(opcode & (1U << base))) @@ -2240,50 +2240,50 @@ static INSN_REGPARM void arm870(u32 opcode) } // STMIA Rn, {Rlist} -static INSN_REGPARM void arm880(u32 opcode) +static INSN_REGPARM void arm880(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; STM_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIA Rn, {Rlist} -static INSN_REGPARM void arm890(u32 opcode) +static INSN_REGPARM void arm890(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); } // STMIA Rn!, {Rlist} -static INSN_REGPARM void arm8A0(u32 opcode) +static INSN_REGPARM void arm8A0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); STMW_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIA Rn!, {Rlist} -static INSN_REGPARM void arm8B0(u32 opcode) +static INSN_REGPARM void arm8B0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); @@ -2292,24 +2292,24 @@ static INSN_REGPARM void arm8B0(u32 opcode) } // STMIA Rn, {Rlist}^ -static INSN_REGPARM void arm8C0(u32 opcode) +static INSN_REGPARM void arm8C0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; STM_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIA Rn, {Rlist}^ -static INSN_REGPARM void arm8D0(u32 opcode) +static INSN_REGPARM void arm8D0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; LDM_ALL_2; LDM_ALL_2B; @@ -2317,26 +2317,26 @@ static INSN_REGPARM void arm8D0(u32 opcode) } // STMIA Rn!, {Rlist}^ -static INSN_REGPARM void arm8E0(u32 opcode) +static INSN_REGPARM void arm8E0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); STMW_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIA Rn!, {Rlist}^ -static INSN_REGPARM void arm8F0(u32 opcode) +static INSN_REGPARM void arm8F0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = reg[base].I & 0xFFFFFFFC; + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = reg[base].I & 0xFFFFFFFC; int count = 0; LDM_ALL_2; if (!(opcode & (1U << base))) @@ -2346,52 +2346,52 @@ static INSN_REGPARM void arm8F0(u32 opcode) } // STMDB Rn, {Rlist} -static INSN_REGPARM void arm900(u32 opcode) +static INSN_REGPARM void arm900(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; STM_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDB Rn, {Rlist} -static INSN_REGPARM void arm910(u32 opcode) +static INSN_REGPARM void arm910(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); } // STMDB Rn!, {Rlist} -static INSN_REGPARM void arm920(u32 opcode) +static INSN_REGPARM void arm920(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; STMW_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDB Rn!, {Rlist} -static INSN_REGPARM void arm930(u32 opcode) +static INSN_REGPARM void arm930(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); @@ -2400,26 +2400,26 @@ static INSN_REGPARM void arm930(u32 opcode) } // STMDB Rn, {Rlist}^ -static INSN_REGPARM void arm940(u32 opcode) +static INSN_REGPARM void arm940(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; STM_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDB Rn, {Rlist}^ -static INSN_REGPARM void arm950(u32 opcode) +static INSN_REGPARM void arm950(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; LDM_ALL_2; LDM_ALL_2B; @@ -2427,26 +2427,26 @@ static INSN_REGPARM void arm950(u32 opcode) } // STMDB Rn!, {Rlist}^ -static INSN_REGPARM void arm960(u32 opcode) +static INSN_REGPARM void arm960(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; STMW_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMDB Rn!, {Rlist}^ -static INSN_REGPARM void arm970(u32 opcode) +static INSN_REGPARM void arm970(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = temp & 0xFFFFFFFC; + uint32_t temp = reg[base].I - 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = temp & 0xFFFFFFFC; int count = 0; LDM_ALL_2; if (!(opcode & (1U << base))) @@ -2456,50 +2456,50 @@ static INSN_REGPARM void arm970(u32 opcode) } // STMIB Rn, {Rlist} -static INSN_REGPARM void arm980(u32 opcode) +static INSN_REGPARM void arm980(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; STM_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIB Rn, {Rlist} -static INSN_REGPARM void arm990(u32 opcode) +static INSN_REGPARM void arm990(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); } // STMIB Rn!, {Rlist} -static INSN_REGPARM void arm9A0(u32 opcode) +static INSN_REGPARM void arm9A0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); STMW_ALL; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIB Rn!, {Rlist} -static INSN_REGPARM void arm9B0(u32 opcode) +static INSN_REGPARM void arm9B0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL; clockTicks += 2 + codeTicksAccess32(armNextPC); @@ -2508,24 +2508,24 @@ static INSN_REGPARM void arm9B0(u32 opcode) } // STMIB Rn, {Rlist}^ -static INSN_REGPARM void arm9C0(u32 opcode) +static INSN_REGPARM void arm9C0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; STM_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIB Rn, {Rlist}^ -static INSN_REGPARM void arm9D0(u32 opcode) +static INSN_REGPARM void arm9D0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL_2; LDM_ALL_2B; @@ -2533,26 +2533,26 @@ static INSN_REGPARM void arm9D0(u32 opcode) } // STMIB Rn!, {Rlist}^ -static INSN_REGPARM void arm9E0(u32 opcode) +static INSN_REGPARM void arm9E0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 0xFF] + cpuBitsSet[(opcode >> 8) & 255]); STMW_ALL_2; clockTicks += 1 + codeTicksAccess32(armNextPC); } // LDMIB Rn!, {Rlist}^ -static INSN_REGPARM void arm9F0(u32 opcode) +static INSN_REGPARM void arm9F0(uint32_t opcode) { if (busPrefetchCount == 0) busPrefetch = busPrefetchEnable; int base = (opcode & 0x000F0000) >> 16; - u32 temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); - u32 address = (reg[base].I + 4) & 0xFFFFFFFC; + uint32_t temp = reg[base].I + 4 * (cpuBitsSet[opcode & 255] + cpuBitsSet[(opcode >> 8) & 255]); + uint32_t address = (reg[base].I + 4) & 0xFFFFFFFC; int count = 0; LDM_ALL_2; if (!(opcode & (1U << base))) @@ -2564,7 +2564,7 @@ static INSN_REGPARM void arm9F0(u32 opcode) // B/BL/SWI and (unimplemented) coproc support //////////////////////////// // B -static INSN_REGPARM void armA00(u32 opcode) +static INSN_REGPARM void armA00(uint32_t opcode) { int offset = opcode & 0x00FFFFFF; if (offset & 0x00800000) @@ -2579,7 +2579,7 @@ static INSN_REGPARM void armA00(u32 opcode) } // BL -static INSN_REGPARM void armB00(u32 opcode) +static INSN_REGPARM void armB00(uint32_t opcode) { int offset = opcode & 0x00FFFFFF; if (offset & 0x00800000) @@ -2596,7 +2596,7 @@ static INSN_REGPARM void armB00(u32 opcode) #ifdef GP_SUPPORT // MRC -static INSN_REGPARM void armE01(u32 opcode) +static INSN_REGPARM void armE01(uint32_t opcode) { } #else @@ -2604,7 +2604,7 @@ static INSN_REGPARM void armE01(u32 opcode) #endif // SWI -static INSN_REGPARM void armF00(u32 opcode) +static INSN_REGPARM void armF00(uint32_t opcode) { clockTicks = codeTicksAccessSeq32(armNextPC) + 1; clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1; @@ -2614,7 +2614,7 @@ static INSN_REGPARM void armF00(u32 opcode) // Instruction table ////////////////////////////////////////////////////// -typedef INSN_REGPARM void (*insnfunc_t)(u32 opcode); +typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode); #define REP16(insn) \ insn, insn, insn, insn, insn, insn, insn, insn, \ insn, insn, insn, insn, insn, insn, insn, insn @@ -2834,7 +2834,7 @@ int armExecute() if ((armNextPC & 0x0803FFFF) == 0x08020000) busPrefetchCount = 0x100; - u32 opcode = cpuPrefetch[0]; + uint32_t opcode = cpuPrefetch[0]; cpuPrefetch[0] = cpuPrefetch[1]; busPrefetch = false; @@ -2855,7 +2855,7 @@ int armExecute() ARM_PREFETCH_NEXT; #ifdef BKPT_SUPPORT - u32 memAddr = armNextPC; + uint32_t memAddr = armNextPC; memoryMap* m = &map[memAddr >> 24]; if (m->breakPoints && BreakARMCheck(m->breakPoints, memAddr & m->mask)) { if (debuggerBreakOnExecution(memAddr, armState)) { diff --git a/src/gba/GBAcpu.h b/src/gba/GBAcpu.h index e48852c1..5386c0ac 100644 --- a/src/gba/GBAcpu.h +++ b/src/gba/GBAcpu.h @@ -20,7 +20,7 @@ extern int thumbExecute(); #define UPDATE_REG(address, value) \ { \ - WRITE16LE(((u16*)&ioMem[address]), value); \ + WRITE16LE(((uint16_t*)&ioMem[address]), value); \ } #define ARM_PREFETCH \ @@ -40,20 +40,20 @@ extern int thumbExecute(); #define THUMB_PREFETCH_NEXT cpuPrefetch[1] = CPUReadHalfWordQuick(armNextPC + 2); extern int SWITicks; -extern u32 mastercode; +extern uint32_t mastercode; extern bool busPrefetch; extern bool busPrefetchEnable; -extern u32 busPrefetchCount; +extern uint32_t busPrefetchCount; extern int cpuNextEvent; extern bool holdState; -extern u32 cpuPrefetch[2]; +extern uint32_t cpuPrefetch[2]; extern int cpuTotalTicks; -extern u8 memoryWait[16]; -extern u8 memoryWait32[16]; -extern u8 memoryWaitSeq[16]; -extern u8 memoryWaitSeq32[16]; -extern u8 cpuBitsSet[256]; -extern u8 cpuLowestBitSet[256]; +extern uint8_t memoryWait[16]; +extern uint8_t memoryWait32[16]; +extern uint8_t memoryWaitSeq[16]; +extern uint8_t memoryWaitSeq32[16]; +extern uint8_t cpuBitsSet[256]; +extern uint8_t cpuLowestBitSet[256]; extern void CPUSwitchMode(int mode, bool saveState, bool breakLoop); extern void CPUSwitchMode(int mode, bool saveState); extern void CPUUpdateCPSR(); @@ -64,7 +64,7 @@ extern void CPUSoftwareInterrupt(); extern void CPUSoftwareInterrupt(int comment); // Waitstates when accessing data -inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ +inline int dataTicksAccess16(uint32_t address) // DATA 8/16bits NON SEQ { int addr = (address >> 24) & 15; int value = memoryWait[addr]; @@ -82,7 +82,7 @@ inline int dataTicksAccess16(u32 address) // DATA 8/16bits NON SEQ return value; } -inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ +inline int dataTicksAccess32(uint32_t address) // DATA 32bits NON SEQ { int addr = (address >> 24) & 15; int value = memoryWait32[addr]; @@ -100,7 +100,7 @@ inline int dataTicksAccess32(u32 address) // DATA 32bits NON SEQ return value; } -inline int dataTicksAccessSeq16(u32 address) // DATA 8/16bits SEQ +inline int dataTicksAccessSeq16(uint32_t address) // DATA 8/16bits SEQ { int addr = (address >> 24) & 15; int value = memoryWaitSeq[addr]; @@ -118,7 +118,7 @@ inline int dataTicksAccessSeq16(u32 address) // DATA 8/16bits SEQ return value; } -inline int dataTicksAccessSeq32(u32 address) // DATA 32bits SEQ +inline int dataTicksAccessSeq32(uint32_t address) // DATA 32bits SEQ { int addr = (address >> 24) & 15; int value = memoryWaitSeq32[addr]; @@ -137,7 +137,7 @@ inline int dataTicksAccessSeq32(u32 address) // DATA 32bits SEQ } // Waitstates when executing opcode -inline int codeTicksAccess16(u32 address) // THUMB NON SEQ +inline int codeTicksAccess16(uint32_t address) // THUMB NON SEQ { int addr = (address >> 24) & 15; @@ -159,7 +159,7 @@ inline int codeTicksAccess16(u32 address) // THUMB NON SEQ } } -inline int codeTicksAccess32(u32 address) // ARM NON SEQ +inline int codeTicksAccess32(uint32_t address) // ARM NON SEQ { int addr = (address >> 24) & 15; @@ -181,7 +181,7 @@ inline int codeTicksAccess32(u32 address) // ARM NON SEQ } } -inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ +inline int codeTicksAccessSeq16(uint32_t address) // THUMB SEQ { int addr = (address >> 24) & 15; @@ -200,7 +200,7 @@ inline int codeTicksAccessSeq16(u32 address) // THUMB SEQ } } -inline int codeTicksAccessSeq32(u32 address) // ARM SEQ +inline int codeTicksAccessSeq32(uint32_t address) // ARM SEQ { int addr = (address >> 24) & 15; @@ -226,10 +226,10 @@ inline int codeTicksAccessSeq32(u32 address) // ARM SEQ inline void cpuMasterCodeCheck() { if ((mastercode) && (mastercode == armNextPC)) { - u32 joy = 0; + uint32_t joy = 0; if (systemReadJoypads()) joy = systemReadJoypad(-1); - u32 ext = (joy >> 10); + uint32_t ext = (joy >> 10); cpuTotalTicks += cheatsCheckKeys(P1 ^ 0x3FF, ext); } } diff --git a/src/gba/gbafilter.cpp b/src/gba/gbafilter.cpp index 325d825f..8dc0d933 100644 --- a/src/gba/gbafilter.cpp +++ b/src/gba/gbafilter.cpp @@ -7,8 +7,8 @@ extern int systemRedShift; extern int systemGreenShift; extern int systemBlueShift; -extern u16 systemColorMap16[0x10000]; -extern u32 systemColorMap32[0x10000]; +extern uint16_t systemColorMap16[0x10000]; +extern uint32_t systemColorMap32[0x10000]; static const unsigned char curve[32] = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1c, 0x20, 0x28, 0x30, 0x38, @@ -27,7 +27,7 @@ inline void swap(short& a, short& b) b = temp; } -void gbafilter_pal(u16* buf, int count) +void gbafilter_pal(uint16_t* buf, int count) { short temp[3 * 3], s; unsigned pix; @@ -101,7 +101,7 @@ void gbafilter_pal(u16* buf, int count) } } -void gbafilter_pal32(u32* buf, int count) +void gbafilter_pal32(uint32_t* buf, int count) { short temp[3 * 3], s; unsigned pix; @@ -205,7 +205,7 @@ void gbafilter_pad(u8* buf, int count) break; case 32: while (count--) { - *((u32*)buf) &= mask.whole; + *((uint32_t*)buf) &= mask.whole; buf += 4; } } diff --git a/src/gba/gbafilter.h b/src/gba/gbafilter.h index bc6cc6cf..69a19dfc 100644 --- a/src/gba/gbafilter.h +++ b/src/gba/gbafilter.h @@ -1,5 +1,5 @@ #include "../System.h" -void gbafilter_pal(u16* buf, int count); -void gbafilter_pal32(u32* buf, int count); -void gbafilter_pad(u8* buf, int count); +void gbafilter_pal(uint16_t* buf, int count); +void gbafilter_pal32(uint32_t* buf, int count); +void gbafilter_pad(uint8_t* buf, int count);