Improve cycle count for MUL, MLA.

Improves Timing score from 679 to 905.
This commit is contained in:
Edênis Freindorfer Azevedo 2020-07-08 16:52:58 -03:00 committed by Edênis Freindorfer Azevedo
parent 7fbb017cd5
commit 9e537a8fe3
1 changed files with 1 additions and 1 deletions

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@ -1251,7 +1251,7 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES)
clockTicks += 3; \
if (busPrefetchCount == 0) \
busPrefetchCount = ((busPrefetchCount + 1) << clockTicks) - 1; \
clockTicks += 1 + codeTicksAccess32(armNextPC);
clockTicks += CYCLES + 1 + codeTicksAccess32(armNextPC);
#define OP_MUL \
reg[dest].I = reg[mult].I * rs;