lets commit the right version of the arm patch this time eh.
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@ -753,8 +753,8 @@ static void count(u32 opcode, int cond_res)
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// OP Rd,Rb,Rm LSL Rs
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#ifndef VALUE_LSL_REG_C
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#define VALUE_LSL_REG_C \
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u32 shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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unsigned int rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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@ -777,7 +777,7 @@ static void count(u32 opcode, int cond_res)
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// OP Rd,Rb,Rm LSR #
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#ifndef VALUE_LSR_IMM_C
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#define VALUE_LSR_IMM_C \
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u32 shift = (opcode >> 7) & 0x1F; \
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unsigned int shift = (opcode >> 7) & 0x1F; \
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if (LIKELY(shift)) { \
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u32 v = reg[opcode & 0x0F].I; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
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@ -791,7 +791,7 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_LSR_REG_C
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#define VALUE_LSR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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unsigned int rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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@ -800,9 +800,8 @@ static void count(u32 opcode, int cond_res)
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value = 0; \
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C_OUT = (rm & 0x80000000 ? true : false); \
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} else if (LIKELY(shift < 32)) { \
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u32 v = rm; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
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value = v >> shift; \
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C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\
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value = rm >> shift; \
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} else { \
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value = 0; \
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C_OUT = false; \
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@ -834,20 +833,19 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_ASR_REG_C
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#define VALUE_ASR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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unsigned int rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift < 32)) { \
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if (LIKELY(shift)) { \
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s32 v = rm; \
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C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
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value = v >> (int)shift; \
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C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\
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value = rm >> (int)shift; \
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} else { \
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value = rm; \
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} \
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} else { \
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if (reg[opcode & 0x0F].I & 0x80000000) { \
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if (rm & 0x80000000) { \
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value = 0xFFFFFFFF; \
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C_OUT = true; \
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} else { \
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@ -876,20 +874,20 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_ROR_REG_C
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#define VALUE_ROR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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unsigned int rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift & 0x1F)) { \
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u32 v = rm; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
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value = ((v << (32 - shift)) | \
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(v >> shift)); \
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C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \
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value = ((rm << (32 - shift)) | \
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(rm >> shift)); \
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} else { \
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value = rm; \
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if (shift) \
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C_OUT = (value & 0x80000000 ? true : false);\
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}#endif
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}
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#endif
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// OP Rd,Rb,# ROR #
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#ifndef VALUE_IMM_C
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#define VALUE_IMM_C \
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