Fix clock cycles in some arm/thumb opcodes.
Implement missing ARM instruction used in the wstein.gba homebrew. Remove cpuDmaHack has it causes graphical glitches in Lufia and incorrectly handles unmapped reads.
This commit is contained in:
parent
0f0d6289d5
commit
56a8cc6e8d
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@ -1533,7 +1533,7 @@ static INSN_REGPARM void arm121(u32 opcode)
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#define OP_LDR reg[dest].I = CPUReadMemory(address)
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#define OP_LDRH reg[dest].I = CPUReadHalfWord(address)
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#define OP_LDRB reg[dest].I = CPUReadByte(address)
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#define OP_LDRSH reg[dest].I = (s16)CPUReadHalfWordSigned(address)
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#define OP_LDRSH reg[dest].I = (u32)CPUReadHalfWordSigned(address)
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#define OP_LDRSB reg[dest].I = (s8)CPUReadByte(address)
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#define WRITEBACK_NONE /*nothing*/
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@ -2608,8 +2608,7 @@ static INSN_REGPARM void armA00(u32 opcode)
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reg[15].I += 4;
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ARM_PREFETCH;
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clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
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clockTicks += 2 + codeTicksAccess32(armNextPC)
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+ codeTicksAccessSeq32(armNextPC);
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clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
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busPrefetchCount = 0;
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}
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@ -2625,8 +2624,7 @@ static INSN_REGPARM void armB00(u32 opcode)
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reg[15].I += 4;
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ARM_PREFETCH;
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clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
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clockTicks += 2 + codeTicksAccess32(armNextPC)
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+ codeTicksAccessSeq32(armNextPC);
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clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
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busPrefetchCount = 0;
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}
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@ -2645,8 +2643,7 @@ static INSN_REGPARM void armE01(u32 opcode)
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static INSN_REGPARM void armF00(u32 opcode)
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{
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clockTicks = codeTicksAccessSeq32(armNextPC) + 1;
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clockTicks += 2 + codeTicksAccess32(armNextPC)
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+ codeTicksAccessSeq32(armNextPC);
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clockTicks = (clockTicks * 2) + codeTicksAccess32(armNextPC) + 1;
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busPrefetchCount = 0;
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CPUSoftwareInterrupt(opcode & 0x00FFFFFF);
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}
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@ -2700,7 +2697,7 @@ static insnfunc_t armInsnTable[4096] = {
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arm0E0,arm0E1,arm0E2,arm0E3,arm0E4,arm0E5,arm0E6,arm0E7, // 0E0
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arm0E0,arm0E9,arm0E2,arm0CB,arm0E4,arm_UI,arm0E6,arm_UI, // 0E8
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arm0F0,arm0F1,arm0F2,arm0F3,arm0F4,arm0F5,arm0F6,arm0F7, // 0F0
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arm0F0,arm0F9,arm0F2,arm_UI,arm0F4,arm0DD,arm0F6,arm0DF, // 0F8
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arm0F0,arm0F9,arm0F2,arm0DB,arm0F4,arm0DD,arm0F6,arm0DF, // 0F8
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arm100,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 100
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arm_UI,arm109,arm_UI,arm10B,arm_UI,arm_UI,arm_UI,arm_UI, // 108
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@ -1421,12 +1421,14 @@ static INSN_REGPARM void thumb45_3(u32 opcode)
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static INSN_REGPARM void thumb46_0(u32 opcode)
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{
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reg[opcode&7].I = reg[((opcode>>3)&7)].I;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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}
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// MOV Rd, Hs
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static INSN_REGPARM void thumb46_1(u32 opcode)
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{
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reg[opcode&7].I = reg[((opcode>>3)&7)+8].I;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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}
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// MOV Hd, Rs
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@ -1473,16 +1475,14 @@ static INSN_REGPARM void thumb47(u32 opcode)
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC)
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+ codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 3;
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clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
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} else {
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armState = true;
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reg[15].I &= 0xFFFFFFFC;
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armNextPC = reg[15].I;
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reg[15].I += 4;
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ARM_PREFETCH;
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clockTicks = codeTicksAccessSeq32(armNextPC)
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+ codeTicksAccessSeq32(armNextPC) + codeTicksAccess32(armNextPC) + 3;
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clockTicks = codeTicksAccessSeq32(armNextPC)*2 + codeTicksAccess32(armNextPC) + 3;
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}
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}
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@ -1576,7 +1576,7 @@ static INSN_REGPARM void thumb5E(u32 opcode)
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if (busPrefetchCount == 0)
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busPrefetch = busPrefetchEnable;
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u32 address = reg[(opcode>>3)&7].I + reg[(opcode>>6)&7].I;
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reg[opcode&7].I = (s16)CPUReadHalfWordSigned(address);
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reg[opcode&7].I = (u32)CPUReadHalfWordSigned(address);
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clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC);
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}
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@ -1669,6 +1669,7 @@ static INSN_REGPARM void thumbA0(u32 opcode)
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{
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u8 regist = (opcode >> 8) & 7;
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reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2);
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clockTicks = 1 + codeTicksAccess16(armNextPC);
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}
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// ADD R0~R7, SP, Imm
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@ -1676,6 +1677,7 @@ static INSN_REGPARM void thumbA8(u32 opcode)
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{
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u8 regist = (opcode >> 8) & 7;
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reg[regist].I = reg[13].I + ((opcode&255)<<2);
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clockTicks = 1 + codeTicksAccess16(armNextPC);
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}
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// ADD SP, Imm
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@ -1685,6 +1687,7 @@ static INSN_REGPARM void thumbB0(u32 opcode)
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if(opcode & 0x80)
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offset = -offset;
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reg[13].I += offset;
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clockTicks = 1 + codeTicksAccess16(armNextPC);
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}
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// Push and pop ///////////////////////////////////////////////////////////
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@ -1882,13 +1885,13 @@ static INSN_REGPARM void thumbC8(u32 opcode)
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static INSN_REGPARM void thumbD0(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(Z_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1897,13 +1900,13 @@ static INSN_REGPARM void thumbD0(u32 opcode)
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static INSN_REGPARM void thumbD1(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!Z_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1912,13 +1915,13 @@ static INSN_REGPARM void thumbD1(u32 opcode)
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static INSN_REGPARM void thumbD2(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(C_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1927,13 +1930,13 @@ static INSN_REGPARM void thumbD2(u32 opcode)
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static INSN_REGPARM void thumbD3(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!C_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1942,13 +1945,13 @@ static INSN_REGPARM void thumbD3(u32 opcode)
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static INSN_REGPARM void thumbD4(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(N_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1957,13 +1960,13 @@ static INSN_REGPARM void thumbD4(u32 opcode)
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static INSN_REGPARM void thumbD5(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!N_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1972,13 +1975,13 @@ static INSN_REGPARM void thumbD5(u32 opcode)
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static INSN_REGPARM void thumbD6(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(V_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -1987,13 +1990,13 @@ static INSN_REGPARM void thumbD6(u32 opcode)
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static INSN_REGPARM void thumbD7(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!V_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2002,13 +2005,13 @@ static INSN_REGPARM void thumbD7(u32 opcode)
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static INSN_REGPARM void thumbD8(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(C_FLAG && !Z_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2017,13 +2020,13 @@ static INSN_REGPARM void thumbD8(u32 opcode)
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static INSN_REGPARM void thumbD9(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!C_FLAG || Z_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2032,13 +2035,13 @@ static INSN_REGPARM void thumbD9(u32 opcode)
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static INSN_REGPARM void thumbDA(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(N_FLAG == V_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2047,13 +2050,13 @@ static INSN_REGPARM void thumbDA(u32 opcode)
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static INSN_REGPARM void thumbDB(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(N_FLAG != V_FLAG) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2062,13 +2065,13 @@ static INSN_REGPARM void thumbDB(u32 opcode)
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static INSN_REGPARM void thumbDC(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC) + 1;
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if(!Z_FLAG && (N_FLAG == V_FLAG)) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2077,13 +2080,13 @@ static INSN_REGPARM void thumbDC(u32 opcode)
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static INSN_REGPARM void thumbDD(u32 opcode)
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{
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UPDATE_OLDREG;
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clockTicks = codeTicksAccessSeq16(armNextPC);
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if(Z_FLAG || (N_FLAG != V_FLAG)) {
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reg[15].I += ((s8)(opcode & 0xFF)) << 1;
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC)+3;
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clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2;
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busPrefetchCount=0;
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}
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}
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@ -2094,8 +2097,8 @@ static INSN_REGPARM void thumbDD(u32 opcode)
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static INSN_REGPARM void thumbDF(u32 opcode)
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{
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u32 address = 0;
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clockTicks = codeTicksAccessSeq16(address) + codeTicksAccessSeq16(address) +
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codeTicksAccess16(address)+3;
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//clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3;
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clockTicks = 3;
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busPrefetchCount=0;
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CPUSoftwareInterrupt(opcode & 0xFF);
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}
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@ -2110,8 +2113,7 @@ static INSN_REGPARM void thumbE0(u32 opcode)
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armNextPC = reg[15].I;
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reg[15].I += 2;
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THUMB_PREFETCH;
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clockTicks = codeTicksAccessSeq16(armNextPC) + codeTicksAccessSeq16(armNextPC) +
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codeTicksAccess16(armNextPC) + 3;
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clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC)+3;
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busPrefetchCount=0;
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}
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@ -2141,8 +2143,7 @@ static INSN_REGPARM void thumbF8(u32 opcode)
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|||
reg[15].I += 2;
|
||||
reg[14].I = temp|1;
|
||||
THUMB_PREFETCH;
|
||||
clockTicks = codeTicksAccessSeq16(armNextPC) +
|
||||
codeTicksAccess16(armNextPC) + codeTicksAccessSeq16(armNextPC) + 3;
|
||||
clockTicks = codeTicksAccessSeq16(armNextPC)*2 + codeTicksAccess16(armNextPC) + 3;
|
||||
busPrefetchCount = 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -42,7 +42,6 @@ bool busPrefetchEnable = false;
|
|||
u32 busPrefetchCount = 0;
|
||||
int cpuDmaTicksToUpdate = 0;
|
||||
int cpuDmaCount = 0;
|
||||
bool cpuDmaHack = false;
|
||||
u32 cpuDmaLast = 0;
|
||||
int dummyAddress = 0;
|
||||
|
||||
|
@ -934,7 +933,7 @@ bool CPUReadGSASnapshot(const char *fileName)
|
|||
fseek(file, 0x0, SEEK_SET);
|
||||
fread(&i, 1, 4, file);
|
||||
fseek(file, i, SEEK_CUR); // Skip SharkPortSave
|
||||
fseek(file, 4, SEEK_CUR); // skip some sort of flag
|
||||
// fseek(file, 4, SEEK_CUR); // skip some sort of flag
|
||||
fread(&i, 1, 4, file); // name length
|
||||
fseek(file, i, SEEK_CUR); // skip name
|
||||
fread(&i, 1, 4, file); // desc length
|
||||
|
@ -1806,8 +1805,8 @@ void CPUSoftwareInterrupt(int comment)
|
|||
case 0x02:
|
||||
#ifdef GBA_LOGGING
|
||||
if(systemVerbose & VERBOSE_SWI) {
|
||||
log("Halt: (VCOUNT = %2d)\n",
|
||||
VCOUNT);
|
||||
/*log("Halt: (VCOUNT = %2d)\n",
|
||||
VCOUNT);*/
|
||||
}
|
||||
#endif
|
||||
holdState = true;
|
||||
|
@ -1817,8 +1816,8 @@ void CPUSoftwareInterrupt(int comment)
|
|||
case 0x03:
|
||||
#ifdef GBA_LOGGING
|
||||
if(systemVerbose & VERBOSE_SWI) {
|
||||
log("Stop: (VCOUNT = %2d)\n",
|
||||
VCOUNT);
|
||||
/*log("Stop: (VCOUNT = %2d)\n",
|
||||
VCOUNT);*/
|
||||
}
|
||||
#endif
|
||||
holdState = true;
|
||||
|
@ -2184,7 +2183,6 @@ void CPUCheckDMA(int reason, int dmamask)
|
|||
doDMA(dma0Source, dma0Dest, sourceIncrement, destIncrement,
|
||||
DM0CNT_L ? DM0CNT_L : 0x4000,
|
||||
DM0CNT_H & 0x0400);
|
||||
cpuDmaHack = true;
|
||||
|
||||
if(DM0CNT_H & 0x4000) {
|
||||
IF |= 0x0100;
|
||||
|
@ -2253,7 +2251,6 @@ void CPUCheckDMA(int reason, int dmamask)
|
|||
DM1CNT_L ? DM1CNT_L : 0x4000,
|
||||
DM1CNT_H & 0x0400);
|
||||
}
|
||||
cpuDmaHack = true;
|
||||
|
||||
if(DM1CNT_H & 0x4000) {
|
||||
IF |= 0x0200;
|
||||
|
@ -2323,7 +2320,6 @@ void CPUCheckDMA(int reason, int dmamask)
|
|||
DM2CNT_L ? DM2CNT_L : 0x4000,
|
||||
DM2CNT_H & 0x0400);
|
||||
}
|
||||
cpuDmaHack = true;
|
||||
|
||||
if(DM2CNT_H & 0x4000) {
|
||||
IF |= 0x0400;
|
||||
|
@ -3404,8 +3400,6 @@ void CPUReset()
|
|||
|
||||
systemSaveUpdateCounter = SYSTEM_SAVE_NOT_UPDATED;
|
||||
|
||||
cpuDmaHack = false;
|
||||
|
||||
lastTime = systemGetClock();
|
||||
|
||||
SWITicks = 0;
|
||||
|
@ -3504,7 +3498,6 @@ void CPULoop(int ticks)
|
|||
|
||||
clockTicks = cpuNextEvent;
|
||||
cpuTotalTicks = 0;
|
||||
cpuDmaHack = false;
|
||||
|
||||
updateLoop:
|
||||
|
||||
|
@ -3906,7 +3899,6 @@ void CPULoop(int ticks)
|
|||
cpuDmaTicksToUpdate -= clockTicks;
|
||||
if(cpuDmaTicksToUpdate < 0)
|
||||
cpuDmaTicksToUpdate = 0;
|
||||
cpuDmaHack = true;
|
||||
goto updateLoop;
|
||||
}
|
||||
|
||||
|
|
|
@ -19,7 +19,6 @@ extern bool cpuSramEnabled;
|
|||
extern bool cpuFlashEnabled;
|
||||
extern bool cpuEEPROMEnabled;
|
||||
extern bool cpuEEPROMSensorEnabled;
|
||||
extern bool cpuDmaHack;
|
||||
extern u32 cpuDmaLast;
|
||||
extern bool timer0On;
|
||||
extern int timer0Ticks;
|
||||
|
@ -49,11 +48,9 @@ static inline u32 CPUReadMemory(u32 address)
|
|||
u32 value;
|
||||
u32 oldAddress = address;
|
||||
|
||||
#ifdef C_CORE
|
||||
if(address & 3) {
|
||||
address &= ~0x03;
|
||||
}
|
||||
#endif
|
||||
|
||||
switch(address >> 24) {
|
||||
case 0:
|
||||
|
@ -133,19 +130,13 @@ unreadable:
|
|||
armNextPC - 4 : armNextPC - 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
if(cpuDmaHack) {
|
||||
value = cpuDmaLast;
|
||||
} else {
|
||||
if(armState) {
|
||||
value = CPUReadMemoryQuick(reg[15].I);
|
||||
return CPUReadMemoryQuick(reg[15].I);
|
||||
} else {
|
||||
value = CPUReadHalfWordQuick(reg[15].I) |
|
||||
return CPUReadHalfWordQuick(reg[15].I) |
|
||||
CPUReadHalfWordQuick(reg[15].I) << 16;
|
||||
}
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
if(oldAddress & 3) {
|
||||
#ifdef C_CORE
|
||||
|
@ -187,11 +178,9 @@ static inline u32 CPUReadHalfWord(u32 address)
|
|||
u32 value;
|
||||
u32 oldAddress = address;
|
||||
|
||||
//#ifdef C_CORE
|
||||
if(address & 1) {
|
||||
address &= ~0x01;
|
||||
}
|
||||
//#endif
|
||||
|
||||
switch(address >> 24) {
|
||||
case 0:
|
||||
|
@ -280,18 +269,13 @@ unreadable:
|
|||
armNextPC - 4 : armNextPC - 2);
|
||||
}
|
||||
#endif
|
||||
if(cpuDmaHack) {
|
||||
value = cpuDmaLast & 0xFFFF;
|
||||
} else {
|
||||
if(armState) {
|
||||
value = CPUReadMemoryQuick(reg[15].I);
|
||||
return CPUReadMemoryQuick(reg[15].I);
|
||||
} else {
|
||||
value = CPUReadHalfWordQuick(reg[15].I) |
|
||||
return CPUReadHalfWordQuick(reg[15].I) |
|
||||
CPUReadHalfWordQuick(reg[15].I) << 16;
|
||||
}
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
if(oldAddress & 1) {
|
||||
value = (value >> 8) | (value << 24);
|
||||
|
@ -306,13 +290,13 @@ unreadable:
|
|||
return value;
|
||||
}
|
||||
|
||||
static inline u16 CPUReadHalfWordSigned(u32 address)
|
||||
static inline s16 CPUReadHalfWordSigned(u32 address)
|
||||
{
|
||||
u32 oldAddress = address;
|
||||
if(address & 1) {
|
||||
address &= ~0x01;
|
||||
}
|
||||
u16 value = CPUReadHalfWord(address);
|
||||
s16 value = (s16)CPUReadHalfWord(address);
|
||||
if((oldAddress & 1))
|
||||
{
|
||||
value = (s8)value;
|
||||
|
@ -395,9 +379,6 @@ unreadable:
|
|||
armNextPC - 4 : armNextPC - 2);
|
||||
}
|
||||
#endif
|
||||
if(cpuDmaHack) {
|
||||
return cpuDmaLast & 0xFF;
|
||||
} else {
|
||||
if(armState) {
|
||||
return CPUReadMemoryQuick(reg[15].I);
|
||||
} else {
|
||||
|
@ -405,8 +386,6 @@ unreadable:
|
|||
CPUReadHalfWordQuick(reg[15].I) << 16;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void CPUWriteMemory(u32 address, u32 value)
|
||||
|
@ -423,6 +402,8 @@ static inline void CPUWriteMemory(u32 address, u32 value)
|
|||
}
|
||||
#endif
|
||||
|
||||
address &= 0xFFFFFFFC;
|
||||
|
||||
switch(address >> 24) {
|
||||
case 0x02:
|
||||
#ifdef BKPT_SUPPORT
|
||||
|
@ -520,6 +501,8 @@ static inline void CPUWriteHalfWord(u32 address, u16 value)
|
|||
}
|
||||
#endif
|
||||
|
||||
address &= 0xFFFFFFFE;
|
||||
|
||||
switch(address >> 24) {
|
||||
case 2:
|
||||
#ifdef BKPT_SUPPORT
|
||||
|
|
Loading…
Reference in New Issue