From 50eea83b1ba4125ee195fe81f307890a33b0e73e Mon Sep 17 00:00:00 2001 From: squall-leonhart Date: Mon, 4 Feb 2013 06:53:17 +0000 Subject: [PATCH] more improvements to gba-arm by Normmatt git-svn-id: https://svn.code.sf.net/p/vbam/code/trunk@1163 a31d4220-a93d-0410-bf67-fe4944624d44 --- src/gba/GBA-arm.cpp | 83 +++++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 40 deletions(-) diff --git a/src/gba/GBA-arm.cpp b/src/gba/GBA-arm.cpp index b95afc82..a146da24 100644 --- a/src/gba/GBA-arm.cpp +++ b/src/gba/GBA-arm.cpp @@ -753,31 +753,31 @@ static void count(u32 opcode, int cond_res) // OP Rd,Rb,Rm LSL Rs #ifndef VALUE_LSL_REG_C #define VALUE_LSL_REG_C \ - unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ - unsigned int rm = reg[opcode & 0x0F].I; \ - if((opcode & 0x0F) == 15) { \ - rm += 4; \ - } \ - if (LIKELY(shift)) { \ - if (shift == 32) { \ - value = 0; \ - C_OUT = (rm & 1 ? true : false);\ - } else if (LIKELY(shift < 32)) { \ - u32 v = rm; \ - C_OUT = (v >> (32 - shift)) & 1 ? true : false;\ - value = v << shift; \ - } else { \ - value = 0; \ - C_OUT = false; \ - } \ - } else { \ - value = rm; \ + u32 shift = reg[(opcode >> 8)&15].B.B0; \ + u32 rm = reg[opcode & 0x0F].I; \ + if((opcode & 0x0F) == 15) { \ + rm += 4; \ + } \ + if (LIKELY(shift)) { \ + if (shift == 32) { \ + value = 0; \ + C_OUT = (rm & 1 ? true : false); \ + } else if (LIKELY(shift < 32)) { \ + u32 v = rm; \ + C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ + value = v << shift; \ + } else { \ + value = 0; \ + C_OUT = false; \ + } \ + } else { \ + value = rm; \ } #endif // OP Rd,Rb,Rm LSR # #ifndef VALUE_LSR_IMM_C #define VALUE_LSR_IMM_C \ - unsigned int shift = (opcode >> 7) & 0x1F; \ + u32 shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ u32 v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ @@ -791,17 +791,18 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_LSR_REG_C #define VALUE_LSR_REG_C \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ - unsigned int rm = reg[opcode & 0x0F].I; \ - if((opcode & 0x0F) == 15) { \ - rm += 4; \ + u32 rm = reg[opcode & 0x0F].I; \ + if((opcode & 0x0F) == 15) { \ + rm += 4; \ } \ if (LIKELY(shift)) { \ if (shift == 32) { \ value = 0; \ - C_OUT = (rm & 0x80000000 ? true : false); \ + C_OUT = (rm & 0x80000000 ? true : false);\ } else if (LIKELY(shift < 32)) { \ - C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\ - value = rm >> shift; \ + u32 v = rm; \ + C_OUT = (v >> (shift - 1)) & 1 ? true : false;\ + value = v >> shift; \ } else { \ value = 0; \ C_OUT = false; \ @@ -833,19 +834,20 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_ASR_REG_C #define VALUE_ASR_REG_C \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ - unsigned int rm = reg[opcode & 0x0F].I; \ - if((opcode & 0x0F) == 15) { \ - rm += 4; \ + u32 rm = reg[opcode & 0x0F].I; \ + if((opcode & 0x0F) == 15) { \ + rm += 4; \ } \ if (LIKELY(shift < 32)) { \ if (LIKELY(shift)) { \ - C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\ - value = rm >> (int)shift; \ + s32 v = rm; \ + C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\ + value = v >> (int)shift; \ } else { \ - value = rm; \ + value = rm; \ } \ } else { \ - if (rm & 0x80000000) { \ + if (reg[opcode & 0x0F].I & 0x80000000) { \ value = 0xFFFFFFFF; \ C_OUT = true; \ } else { \ @@ -874,16 +876,17 @@ static void count(u32 opcode, int cond_res) #ifndef VALUE_ROR_REG_C #define VALUE_ROR_REG_C \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ - unsigned int rm = reg[opcode & 0x0F].I; \ - if((opcode & 0x0F) == 15) { \ - rm += 4; \ + u32 rm = reg[opcode & 0x0F].I; \ + if((opcode & 0x0F) == 15) { \ + rm += 4; \ } \ if (LIKELY(shift & 0x1F)) { \ - C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \ - value = ((rm << (32 - shift)) | \ - (rm >> shift)); \ + u32 v = rm; \ + C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ + value = ((v << (32 - shift)) | \ + (v >> shift)); \ } else { \ - value = rm; \ + value = rm; \ if (shift) \ C_OUT = (value & 0x80000000 ? true : false);\ }